JAJSGL5C December   2018  – August 2019 TPS3840

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
      2.      TPS3840 の標準的な消費電流
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage (VDD)
        1. 9.3.1.1 VDD Hysteresis
        2. 9.3.1.2 VDD Transient Immunity
      2. 9.3.2 User-Programmable Reset Time Delay
      3. 9.3.3 Manual Reset (MR) Input
      4. 9.3.4 Output Logic
        1. 9.3.4.1 RESET Output, Active-Low
        2. 9.3.4.2 RESET Output, Active-High
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation (VDD > VDD(min))
      2. 9.4.2 VDD Between VPOR and VDD(min)
      3. 9.4.3 Below Power-On-Reset (VDD < VPOR)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
      4. 10.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
      5. 10.2.5 Application Curve: TPS3840EVM
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイスの項目表記
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 Timing Requirements

At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted. Typical values are at TJ = 25°C. 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSTRT Startup Delay(1) CT pin open 100 220 350 µs
tP_HL Propagation detect delay for VDD falling below VIT- VDD = VIT+ to (VIT-) - 10%(2) 15 30 µs
tD Reset time delay CT pin = open
 		 50 µs
CT pin = 10 nF 6.2 ms
CT pin = 1 µF 619 ms
tGI_VIT- Glitch immunity VIT- 5% VIT- overdrive(3) 10 µs
tMR_PW MR pin pulse duration to initiate reset 300 ns
tMR_RES Propagation delay from MR low to reset VDD = 4.5 V, MR < VMR_L 700 ns
tMR_tD Delay from release MR to deasert reset VDD = 4.5 V,
MR = VMR_L to VMR_H   		tD ms
(1) When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is release after the startup delay (tSTRT), a capacitor at CT pin will add tD delay to tSTRT time
(2) tP_HL measured from threhold trip point (VIT-) to VOL for active low variants and VOH for active high variants. 
(3) Overdrive % = [(VDD/ VIT-) - 1] × 100%
TPS3840 TD-TPS3840DL-Rev5.gif
1. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time will be added to the startup time, VDD slew rate = 100 mV / µs.
2. Open-Drain timing diagram assumes pull-up resistor is connected to RESET
3. RESET output is undefined when VDD is < VPOR
Figure 3. Timing Diagram TPS3840DL (Open-Drain Active-Low)
TPS3840 TD-TPS3840PL-Rev6.gif
1. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then tD programmed time will be added to the startup time. VDD slew rate = 100 mV / µs.
2. RESET output is undefined when VDD < VPOR and limited to VOL for VDD slew rate = 100 mV / µs
Figure 4. Timing Diagram TPS3840PL (Push-Pull Active-Low)
TPS3840 TD-TPS3840PH-Rev4.gif
1. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then tD programmed time will be added to the total startup time. VDD slew rate = 100 mV / µs.
Figure 5. Timing Diagram TPS3840PH (Push-Pull Active-High)