JAJSCT5A March 2016 – May 2016 TPS3890
|5||CT||—|| The CT pin offers a user-adjustable delay time. Connecting this pin to a ground-referenced capacitor sets the RESET delay time to deassert.
tPD(r) (sec) = CCT (µF) × 1.07 + 25 µs (nom).
|3||MR||I||Driving the manual reset pin (MR) low causes RESET to go low (assert).|
|6||RESET||O||RESET is an open-drain output that is driven to a low-impedance state when either the MR pin is driven to a logic low or the monitored voltage on the SENSE pin is lower than the negative threshold voltage (VITN). RESET remains low (asserted) for the delay time period after both MR is set to a logic high and the SENSE input is above VITP. A pullup resistor from 10 kΩ to 1 MΩ can be used on this pin.|
|1||SENSE||I||This pin is connected to the voltage to be monitored. When the voltage on SENSE falls below the negative threshold voltage VITN, RESET goes low (asserts). When the voltage on SENSE rises above the positive threshold voltage VITP, RESET goes high (deasserts).|
|4||VDD||I||Supply voltage pin. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.|