The TPS3899 voltage supervisor with push-button monitor asserts a RESET/RESET signal when the SENSE pin voltage drops below V_IT- for the duration of the sense delay set by CTS. If the SENSE pin voltage rises above V_IT- + V_HYS before the sense delay expires, the RESET/RESET pin does not assert. When asserted, the RESET/RESET output remains asserted until SENSE voltage returns above V_IT- + V_HYS for the duration of the reset delay set by CTR. If the SENSE pin voltage falls below V_IT- before the reset delay expires while RESET is asserted, RESET/RESET will remain asserted.

Like most voltage supervisors, the TPS3899 includes a reset delay t_D to provide time for the power and clocks to settle before letting the processor out of reset. At power up, the circuits inside the TPS3899 need additional time to start the reset delay timer after its power supply VDD has reached minimum V_DD(MIN) for these circuits to start operating properly. This additional time is specified with the parameter start-up delay t_STRT. Figure 5-1 shows the timing diagram indicating this additional delay. After VDD is stable and above V_DD(MIN) subsequent changes of the sense voltage across the threshold voltage will trigger reset after only the reset delay. The reset time delay t_D is set by a capacitor on the CTR pin. The start-up delay has a max spec limit of 300μs for a ramp rate of
V_DD ≤ 1V/μS.