JAJSIJ2C September   2020  – January 2024 TPS3899

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6.   Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD Hysteresis
      2. 6.3.2 User-Programmable Sense and Reset Time Delay
      3. 6.3.3 RESET/RESET Output
      4. 6.3.4 SENSE Input
        1. 6.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation (VDD > VDD(min))
      2. 6.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 6.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. 7.2.5.1 Layout Guidelines
        2. 7.2.5.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2 Detailed Design Procedure

The TPS3899DL01 can monitor any voltage above 0.505V using an external voltage divider. This device has a negative going input threshold voltage of 0.505V; however, the design needs to assert a reset when VDD drops below 2.9V. By using a resistor divider (R1 = 47.5kΩ, R2 = 10kΩ) the negative going threshold voltage becomes 2.93V. The device's positive going voltage threshold is VIT- + VHYS. The typical VHYS is 25.5mV. This in combination with the resistor divider makes the design's positive going threshold voltage equal to 3.08V. If VDD falls below 2.93V for the duration of sense delay (tD-SENSE), the reset asserts. If VDD rises above 3.08V for the duration of reset delay (tD), the reset deasserts. See Figure 7-2 for a timing diagram detailing the voltage levels and reset assertion/deassertion conditions.

GUID-20200902-CA0I-VRZD-0SPQ-3XRD8MR0J7XQ-low.svg Figure 7-2 Design 1 Timing Diagram

This design also enters a reset condition when the push-button (PB) is asserted. The push-button is tied to ground and when pressed drops the SENSE voltage to 0V, making the device assert a reset. As a good analog practice, a 0.1µF capacitor was also placed on VDD.

The desired reset timing conditions are sense delay time of 60ms (the time to trigger a reset) and a reset delay time of 60ms (the time to recover from a reset). Using Equation 4 and Equation 5, respectively, to solve for CTS and CTR capacitor values, CTS = 0.1µF and CTR = 0.1µF. These capacitor values give a nominal sense delay time of 62ms and nominal reset delay time of 62ms. Figure 7-3 and
Figure 7-4 are the results of the described application where the measured sense and reset delay time are shown respectively.

For the requirement of a maximum output current, an external pull-up resistor needs to be selected so that the current through the external pull-up resistor exceeds no more than 500µA. When the reset output is low, the voltage drop across the external pull-up resistor is equal to VDD. Ohm’s law is used to calculate the minimum resistor value. The resistor needs to be greater than 6kΩ to pull less than 500µA in the reset asserted low condition. A resistor value of 10kΩ was selected to accomplish this.

Note that this design does not account for tolerances.