JAJSGE0C JANUARY   2014  – October 2018 TPS40425

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1. 3.1 アプリケーション概略図 （デュアル出力）
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Asynchronous Pulse Injection (API)
      2. 7.3.2  Adaptive Voltage Scaling (AVS)
      3. 7.3.3  Switching Frequency and Synchronization
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Output Voltage and Remote Sensing Amplifier
      6. 7.3.6  Current Sensing and Temperature Sensing Modes
        1. 7.3.6.1 Non Smart-Power Operation
        2. 7.3.6.2 Smart-Power Operation.
      7. 7.3.7  Current Sensing
      8. 7.3.8  Temperature Sensing
      9. 7.3.9  Current Sharing
      10. 7.3.10 Linear Regulators
      11. 7.3.11 Power Sequence Between TPS40425 Device and Power Stage
      12. 7.3.12 PWM Signal
        1. 7.3.12.1 PWM Behavior During Soft-start Operation
      13. 7.3.13 Startup and Shutdown
      14. 7.3.14 Pre-Biased Output Start-up
      15. 7.3.15 PGOOD Indication
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Overvoltage/Undervoltage Protection
      18. 7.3.18 Overtemperature Fault Protection
      19. 7.3.19 Input Undervoltage Lockout (UVLO)
      20. 7.3.20 Fault Communication
      21. 7.3.21 Fault Protection Summary
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Multi-Phase Applications
    6. 7.6 Register Maps
      1. 7.6.1 PMBus General Description
      2. 7.6.2 PMBus Functionality
        1. 7.6.2.1 PMBus Address
        2. 7.6.2.2 PMBus Connections
        3. 7.6.2.3 PMBus Data Format
        4. 7.6.2.4 PMBus Output Voltage Adjustment
          1. 7.6.2.4.1 No Margin Voltage
          2. 7.6.2.4.2 Margin High Voltage State
          3. 7.6.2.4.3 Margin Low State
      3. 7.6.3 Reading the Output Current
      4. 7.6.4 Soft-Start Time
      5. 7.6.5 Turn-On/Turn-Off Delay and Sequencing
    7. 7.7 Supported PMBus Commands
      1. 7.7.1  PAGE (00h)
      2. 7.7.2  OPERATION (01h)
      3. 7.7.3  ON_OFF_CONFIG (02h)
      4. 7.7.4  CLEAR_FAULTS (03h)
      5. 7.7.5  WRITE_PROTECT (10h)
      6. 7.7.6  STORE_USER_ALL (15h)
      7. 7.7.7  RESTORE_USER_ALL (16h)
      8. 7.7.8  CAPABILITY (19h)
      9. 7.7.9  VOUT_MODE (20h)
      10. 7.7.10 VIN_ON (35h)
      11. 7.7.11 VIN_OFF (36h)
      12. 7.7.12 IOUT_CAL_GAIN (38h)
      13. 7.7.13 IOUT_CAL_OFFSET (39h)
      14. 7.7.14 IOUT_OC_FAULT_LIMIT (46h)
      15. 7.7.15 IOUT_OC_FAULT_RESPONSE (47h)
      16. 7.7.16 IOUT_OC_WARN_LIMIT (4Ah)
      17. 7.7.17 OT_FAULT_LIMIT (4Fh)
      18. 7.7.18 OT_WARN_LIMIT (51h)
      19. 7.7.19 TON_RISE (61h)
      20. 7.7.20 STATUS_BYTE (78h)
      21. 7.7.21 STATUS_WORD (79h)
      22. 7.7.22 STATUS_VOUT (7Ah)
      23. 7.7.23 STATUS_IOUT (7Bh)
      24. 7.7.24 STATUS_TEMPERATURE (7Dh)
      25. 7.7.25 STATUS_CML (7Eh)
      26. 7.7.26 STATUS_MFR_SPECIFIC (80h)
      27. 7.7.27 READ_VOUT (8Bh)
      28. 7.7.28 READ_IOUT (8Ch)
      29. 7.7.29 READ_TEMPERATURE_2 (8Eh)
      30. 7.7.30 PMBus_REVISION (98h)
      31. 7.7.31 MFR_SPECIFIC_00 (D0h)
      32. 7.7.32 MFR_SPECIFIC_04 (VREF_TRIM) (D4h)
      33. 7.7.33 MFR_SPECIFIC_05 (STEP_VREF_MARGIN_HIGH) (D5h)
      34. 7.7.34 MFR_SPECIFIC_06 (STEP_VREF_MARGIN_LOW) (D6h)
      35. 7.7.35 MFR_SPECIFIC_07 (PCT_VOUT_FAULT_PG_LIMIT) (D7h)
      36. 7.7.36 MFR_SPECIFIC_08 (SEQUENCE_TON_TOFF_DELAY) (D8h)
      37. 7.7.37 MFR_SPECIFIC_16 (COMM_EEPROM_SPARE) (E0h)
      38. 7.7.38 MFR_SPECIFIC_21 (OPTIONS) (E5h)
      39. 7.7.39 MFR_SPECIFIC_22 (PWM_OSC_SELECT) (E6h)
      40. 7.7.40 MFR_SPECIFIC_23 (MASK SMBALERT) (E7h)
      41. 7.7.41 MFR_SPECIFIC_25 (AVS_CONFIG) (E9h)
      42. 7.7.42 MFR_SPECIFIC_26 (AVS_ADDRESS) (EAh)
      43. 7.7.43 MFR_SPECIFIC_27 (AVS_DAC_DEFAULT) (EBh)
      44. 7.7.44 MFR_SPECIFIC_28 (AVS_CLAMP_HI) (ECh)
      45. 7.7.45 MFR_SPECIFIC_29 (AVS_CLAMP_LO) (EDh)
      46. 7.7.46 MFR_SPECIFIC_30 (TEMP_OFFSET) (EEh)
      47. 7.7.47 MFR_SPECIFIC_32 (API_OPTIONS) (F0h)
      48. 7.7.48 MFR_SPECIFIC_44 (DEVICE_CODE) (FCh)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Dual-Output Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Design Procedure
        1. 8.2.3.1  Switching Frequency Selection
        2. 8.2.3.2  Inductor Selection
        3. 8.2.3.3  Output Capacitor Selection
          1. 8.2.3.3.1 Output Voltage Deviation During Load Transient
          2. 8.2.3.3.2 Output Voltage Ripple
        4. 8.2.3.4  Input Capacitor Selection
        5. 8.2.3.5  VDD, BP5, BP3 Bypass Capacitor
        6. 8.2.3.6  R-C Snubber
        7. 8.2.3.7  Current and Temperature Sensor
        8. 8.2.3.8  Power Sequence Between the TPS40425 Device and Power Stage
        9. 8.2.3.9  Output Voltage Setting and Frequency Compensation Selection
        10. 8.2.3.10 Key PMBus Parameter Selection
          1. 8.2.3.10.1 MFR_SPECIFIC_21 (OPTIONS)
            1. 8.2.3.10.1.1 IOUT_CAL_GAIN
            2. 8.2.3.10.1.2 Enable and UVLO
            3. 8.2.3.10.1.3 Soft-Start Time
            4. 8.2.3.10.1.4 Overcurrent Threshold and Response
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Guidelines for TPS40425 Device
      2. 10.1.2 Layout Guidelines for Power Stage Device
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 Texas Instruments Fusion Digital Power Designer
        2. 11.1.1.2 TPS40kループ補償ツール
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.1 Multi-Phase Applications

TPS40425 ai_2_phase_schem_slusbo6.gifFigure 20. Typical 2-Phase Application Schematic

Table 4. Pin Configurations for Dual Output and 2-Phase Operation

PIN NAME DUAL OUTPUT 2-PHASE
RT Connecting a resistor from this pin to AGND Connecting a resistor from this pin to AGND
SYNC Floating or connect to external clock Floating or connect to external clock
PHSET Floating Floating
FB1 Inverting input to the error amplifier 1 Inverting input to the error amplifier 1
FB2 Inverting input to the error amplifier 2 Connect to BP5
COMP1 Output of the error amplifier 1 Output of the error amplifier 1, connect to COMP bus
COMP2 Output of the error amplifier 2 Connect to COMP bus
ISH1 Floating Connect to ISH bus
ISH2 Floating Connect to ISH bus
FLT1 Fault inductor of CH1 Connect to FLT bus
FLT2 Fault inductor of CH2 Connect to FLT bus
PG1 Power good indicator for CH1 output voltage, connect to BP5 via a pull-up resistor Power good indicator for 2-phase output voltage, connect to BP5 via a pull-up resistor
PG2 Power good indicator for CH2 output voltage, connect to BP5 via a pull-up resistor Floating or connect to GND
VSENS1 Positive pin of Voltage Sense Signal for CH1 Positive pin of Voltage Sense Signal for 2-phase output
GSENS1 Negative pin of Voltage Sense Signal for CH1 Negative pin of Voltage Sense Signal for 2-phase output
VSENS2 Positive pin of Voltage Sense Signal for CH2 Connect to GND is recommended. Connect to the output voltage is also allowed.
GSENS2 Negative pin of Voltage Sense Signal for CH2 Connect to GND
CNTL1 Logic level input which starts or stops CH1 Logic level input which starts or stops both channels.
CNTL2 Logic level input which starts or stops CH2 Floating
DIFFO1 Remote Sense Amplifier Output for CH1 Remote Sense Amplifier Output for 2-phase
AVSDATA AVS data(1) AVS data for 2-phase(1)
AVSCLK AVS CLOCK(1) AVS CLOCK for 2-phase(1)
(1) If AVS mode is disabled in both channels, AVSDATA and AVSCLK pins can be either floating or connecting to GND. If AVS mode is enabled and AVS interface is used in either channel, AVSDATA and AVSCLK must to connected to AVS host. If AVS mode is enabled and AVS_STARTUP mode is used in either channel, AVSDATA and AVSCLD must be connected to GND or a bias voltage. Refer to the MFR_SPECIFIC_16 (COMM_EEPROM_SPARE) (E0h) section for more information.

Table 5. Pin Configurations for 3-Phase and 4-Phase Operation(1)

DEVICE PIN NAME 3-PHASE 4-PHASE
IC1

(Master)		 RT Connecting a resistor from this pin to AGND, use the same RT resistor value for IC1 and IC2 Connecting a resistor from this pin to AGND, use the same RT resistor value for IC1 and IC2
SYNC Connect to SYNC bus Connect to SYNC bus
PHSET Connect to PHSET bus Connect to PHSET bus
FB1 Inverting input to the error amplifier 1 of IC1 Inverting input to the error amplifier 1 of IC1
FB2 Connect to BP5 of IC1 Connect to BP5 of IC1
COMP1 Output of the error amplifier 1of IC1, connect to COMP bus Output of the error amplifier 1 OF IC1, Connect to COMP bus
COMP2 Connect to COMP bus Connect to COMP bus
ISH1 Connect to ISH bus Connect to ISH bus
ISH2 Connect to ISH bus Connect to ISH bus
FLT1 Connect to FLT bus Connect to FLT bus
FLT2 Connect to FLT bus Connect to FLT bus
PG1 Power good indicator for 3-phase output voltage, connect to BP5 via a pull-up resistor Power good indicator for 4-phase output voltage, connect to BP5 via a pull-up resistor
PG2 Floating or connect to GND Floating or connect to GND
VSENS1 Positive pin of Voltage Sense Signal for 3-phase output Positive pin of Voltage Sense Signal for 4-phase output
GSENS1 Negative pin of Voltage Sense Signal for 3-phase output Negative pin of Voltage Sense Signal for 4-phase output
VSENS2 Connect to GND is recommended. Connect to the output voltage is also allowed. Connect to GND is recommended. Connect to the output voltage is also allowed.
GSENS2 Connect to GND Connect to GND
CNTL1 Logic level input which starts or stops 3-phase Logic level input which starts or stops 4-phase
CNTL2 Floating Floating
DIFFO1 Remote Sense Amplifier Output for 3-phase Remote Sense Amplifier Output for 4-phase
AVSDATA AVS data for 3-phase(1) AVS data for 4-phase(1)
AVSCLK AVS CLOCK for 3-phase(1) AVS CLOCK for 4-phase(1)
IC2

(Slave)		 RT Connecting a resistor from this pin to AGND, use the same RT resistor value for IC1 and IC2 Connecting a resistor from this pin to AGND, use the same RT resistor value for IC1 and IC2
SYNC Connect to SYNC bus Connect to SYNC bus
PHSET Connect to PHSET bus Connect to PHSET bus
FB1 Connect to BP5 of IC2 Connect to BP5 of IC2
FB2 Inverting input to the error amplifier 2 of IC2 Connect to BP5 of IC2
COMP1 Connect to COMP bus Connect to COMP bus
COMP2 Output of the error amplifier 2 of IC2 Connect to COMP bus
ISH1 Connect to ISH bus Connect to ISH bus
ISH2 Floating Connect to ISH bus
FLT1 Connect to FLT bus Connect to FLT bus
FLT2 Fault indicator for CH2 of IC2 Connect to FLT bus
PG1 Floating or connect to GND Floating or connect to GND
PG2 Power good indicator for CH2 output voltage of IC2, connect to BP5 via a pull-up resistor Floating or connect to GND
VSENS1 Connect to GND is recommended. Connection to the output voltage is also allowed. Connect to GND is recommended. Connection to the output voltage is also allowed.
GSENS1 Connect to GND Connect to GND
VSENS2 Positive pin of Voltage Sense Signal for CH2 of IC2 Connect to GND is recommended. Connect to the output voltage is also allowed.
GSENS2 Negative pin of Voltage Sense Signal for CH2 of IC2 Connect to GND
CNTL1 Connect to CNTL1 of IC1 Connect to CNTL1 of IC1
CNTL2 Logic level input which starts or stops CH2 of IC2 Floating
DIFFO1 Floating Floating
AVSDATA Can be used for CH2 of IC2.(1) See (1)
AVSCLK Can be used for CH2 of IC2.(1) See (1)
(1) If one channel is not used, that channel related pins need to be connected as below table shows to avoid any damage due to noise coupling.

Table 6. Configurations of Unused Pins

PIN NAME NON SMART-POWER MODE SMART-POWER MODE
SYNC Floating Floating
PHSET Floating Floating
CNTLx Connect to GND or logic high voltage whichever turns PWM off. Connect to GND or logic high voltage whichever turns PWM off.
SMBALERT Pull up to BP3 via 100-kΩ resistor Pull up to BP3 via 100-kΩ resistor
PMBDATA Pull up to BP3 via 100-kΩ resistor Pull up to BP3 via 100-kΩ resistor
PMBCLK Pull up to BP3 via 100-kΩ resistor Pull up to BP3 via 100-kΩ resistor
AVSDATA Floating or connect to GND if AVS mode is disabled. Connect to GND is recommended. Floating or connect to GND if AVS mode is disabled. Connect to GND is recommended.
AVSCLK Floating or connect to GND if AVS mode is disabled. Connect to GND is recommended. Floating or connect to GND if AVS mode is disabled. Connect to GND is recommended.
VSENSx Connect to GND is recommended. Connect to the output voltage is also allowed. Connect to GND is recommended. Connect to the output voltage is also allowed.
GSENSx Connect to GND Connect to GND
COMPx Floating Floating
FBx Connect to GND Connect to GND
FLTx Floating Floating
CSxP Connect to GND Connect to CSxN only
CSxN Connect to GND Connect to CSxP only
TSNSx Floating Connect to GND
ISHx Floating Floating
PGx Connect to GND Connect to GND
PWMx Floating Floating
DIFFO1 Floating Floating