JAJSGE0C JANUARY 2014 – October 2018 TPS40425
PRODUCTION DATA.
| Format | Unsigned binary | ||||
| Description | This register is used for setting user selectable AVS configuration (AVS enable, double transmission check, payload size, and VREF slew-rate). | ||||
| Default | 0002h
The default power-up state can be changed using the STORE_USER commands. |
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| PAGE0, PAGE1 | |||||||||||||||
| r/wE | r | r | r | r | r | r | r | r | r | r/wE | r/wE | r/wE | r/wE | r/wE | r/wE |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AVS_EN | AVS_IO | AVS_STUP | TX2 | PAYLOAD<1:0> | SLEW | ||||||||||
| Bits | Field Name | Description |
|---|---|---|
| 7 | AVS_EN | (Format: binary)
Default: 0b AVS mode enable This bit, when high, enables the AVS mode of operation. Otherwise, the IC operates in the non-AVS mode. All other AVS commands (in effect, MFR_SPECIFIC_26, MFR_SPECIFIC_27, MFR_SPECIFIC_28, and MFR_SPECIFIC_29) are write-disabled (read-only access) in the AVS mode. An attempt to write to any of these registers in the AVS mode results in the “oth” bit in STATUS_CML to be set and SMBALERT to be declared. (MFR_SPECIFIC_27 has a slight exception here, as it is writeable in AVS_STARTUP mode). Also, the following PMBus commands related to VREF_TRIM and MARGIN are disabled (both read and write) and NACK’d in the AVS mode: MFR_04 (D4h) VREF_TRIM MFR_05 (D5h) STEP_VREF_MARGIN_HIGH MFR_06 (D6h) STEP_VREF_MARGIN_LOW To change this value, the user must change this value in the register, save it to the EEPROM and then reboot the device via power down for the new value to take effect. 0: PMBus mode enabled 1: AVS mode enabled |
| 6:0
7:6 |
Note: Any values written to read-only registers are ignored. | |
| 5 | AVS_IO | (Format: binary)
Default: 0b AVS I/O adjust This bit, when high, changes the internal logic level detection circuit (sensing the AVS_CLK and AVS_DATA signals at the IC pins) from 2.5 V to 1.8 V. This signal is only defined on PAGE 0 (channel 1). Since there is a single AVS interface to TPS40425, the setting here effectively applies to both channels. The corresponding bit on PAGE 1 is read-only and set to a default of 0. 0: AVS CLK and DATA signals from ASIC are at 2.5-V logic 1: AVS CLK and DATA signals from ASIC are at 1.8-V logic |
| 4 | AVS_STUP | (Format: binary)
Default: 0b AVS startup mode enable This bit when high enables a mode called AVS_STARTUP mode, which is a sub-mode of the AVS mode. The AVS_STARTUP mode can only be enabled when the channel is in the AVS mode (in effect, it cannot be enabled in the non-AVS mode, even if the AVS_STUP bit is set high.). There are a few key features of the AVS_STARTUP mode: MMMa. When in the AVS mode, the user can change to and from the AVS_STARTUP mode “on-the-fly” by simply changing the state of the AVS_STUP bit, without having to power-cycle the part MMMb. When in the AVS_STARTUP mode, the reference voltage VREF is determined by the contents of MFR_27 (EBh). The slew rate of VREF is controlled by TON_RISE or AVS_SLEW, depending on what operating state the channel is in: MMMMo While on SoftStart, Slew rate is controlled by TON_RISE. MMMMo After SoftStart (this is Normal Operation), Slew rate is controlled by AVS_SLEW (MFR25[0]). MMMc. When in the AVS_STARTUP mode, the user can change the contents of MFR_27 (EB) by PMBus to enable the control of the VREF by PMBus MMMd. When in the AVS_STARTUP mode, all commands on the AVS bus are ignored. |
| 3 | TX2 | (Format: binary)
Default: 0b AVS Double Transmission Check Select This bit is used to force the AVS slave to require any AVS command to be issued twice before it is acted upon. 0: Every commit-write actually takes effect as indicated by the AVS Master. 1: Every commit-write attempt must be performed twice for it to take effect. This bit should not change while AVS is enabled. |
| 2:1 | PAYLOAD<1:0> | (Format: binary)
Default: 01b AVS Payload Configuration This bit-field determines the number of bits that the device uses for sending “Voltage” in an AVS read frame, as well as the number of bits that the device expects in an AVS write frame. Considering that TPS40425’s encoding for the DAC voltage requires 10 bits, the setting for 8 bits is not acceptable . 00: 8-bit voltage – Reserved, not to be used in TPS40425. 01: 10-bit voltage, the minimum size (and the default setting). 10: 12-bit voltage. Allowed. 11: 16-bit voltage. Allowed. This bit field should not change while AVS is enabled. |
| 0 | SLEW | (Format: binary)
Default: 0b AVS Slew rate select This bit is used to select between fast (default) and slow AVS transition rates by adjusting the slew rate of the error-amplifier reference voltage VREF. 0: Fast AVS slew rate selected (200 mV / 30 µs) 1: Slow AVS rate selected (2 mV / 30 µs – slowest soft-start rate) |
Table 15 summarizes the various mode transitions.
| INITIAL MODE | INPUT
CONDITIONS |
IF THIS EVENT
OCCURS |
FINAL
MODE |
|
|---|---|---|---|---|
| AVS_EN | AVS_STUP | |||
| AVS | X | X | No power-cycle | AVS |
| AVS | 1 | 0 | Power cycle | AVS |
| AVS | 1 | 1 | Power cycle | AVS_STARTUP |
| AVS | 0 | X | Power cycle | PMBus |
| AVS | X | 1 | No power cycle | AVS_STARTUP |
| AVS_STARTUP | X | 1 | No power cycle | AVS_STARTUP |
| AVS_STARTUP | 1 | 0 | With or without power cycle | AVS |
| AVS_STARTUP | 1 | 1 | Power cycle | AVS_STARTUP |
| AVS_STARTUP | 0 | X | Power cycle | PMBus |
| PMBus | X | X | No power cycle | PMBus |
| PMBus | 0 | X | Power cycle | PMBus |
| PMBus | 1 | 0 | Power cycle | AVS |
| PMBus | 1 | 1 | Power cycle | AVS_STARTUP |