SLUSBA6B December   2012  – October 2015 TPS51604

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
    7. 6.7 Typical Power Block MOSFET Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO Protection
      2. 7.3.2 PWM Pin
      3. 7.3.3 SKIP Pin
        1. 7.3.3.1 Zero Crossing (ZX) Operation
      4. 7.3.4 Adaptive Dead-Time Control and Shoot-Through Protection
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step 1: Select the Input (VDD) Capacitor
        2. 8.2.2.2 Step 2: Select Boot Capacitor and Boot Resistor
        3. 8.2.2.3 Step 3: Establish Connection Between TPS51604 and Controller
        4. 8.2.2.4 Step 4: Establish Connection Between TPS51604 and the Power Block
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS51604 driver is optimized for high-frequency CPU VCORE applications. Advanced features such reduced dead-time drive and Auto Zero Crossing are used to optimize efficiency over the entire load range.

8.2 Typical Application

Figure 19 and Figure 20 show a 2-phase design example where TPS51604 device works with the TPS51632 controller and the CSD87381 power block.

TPS51604 pmp9128_main_slusba6.gif Figure 19. Controller Schematic
TPS51604 pmp9128_aux_slusba6.gif Figure 20. Driver, Power Block, and Output Stage Schematic

8.2.1 Design Requirements

The design example uses the input parameters summarized in Table 2.

Table 2. Design Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 6 12 20 V
VOUT Output voltage 1.2 V
VP_P Output ripple voltage IOUT = 12 A 20 mV
IOUT Output current 0 12 A
η Efficiency IOUT = 12 A, VIN - 12 V 80%
fSW Switching frequency 1000 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Step 1: Select the Input (VDD) Capacitor

A 5-V power supply is suggested for VDD. Placed a ceramic capacitor with a value of 1 uF or greater between VDD and GND.

8.2.2.2 Step 2: Select Boot Capacitor and Boot Resistor

The boot capacitor is the power supply for high-side driver. Place a ceramic capacitor with a value of 0.1 µF or greater between the BST pin and the SW pin.

To reduce the voltage spike on switch node, use a boot resistor with a value of several Ohms in series with boot capacitor to slow the turn-on of high-side FET.

8.2.2.3 Step 3: Establish Connection Between TPS51604 and Controller

Connect the PWM pin of the TPS51604 device to the PWM pin of the controller. The TRIP pins can be used for DCM mode or very-low-power state. Leave the TRIP pin floating if it is not in use.

8.2.2.4 Step 4: Establish Connection Between TPS51604 and the Power Block

Connect the DRVH pin of the TPS51604 device to the gate of the high-side FET of the power block. Connect the DRVL pin of the TPS51604 device to the gate of the low-side FET of the power block. Connect the SW pins of the TPS51604 device to the switch node as required by the high-side driver fo the power block.

8.2.3 Application Curves

TPS51604 en_waveform_slusba6.png
VIN = 12 V IOUT = 0 A
Figure 21. Enable Turn-on
TPS51604 D002_SLUSBA6.gif
fSW = 1 MHz
Figure 23. Efficiency vs. Load
TPS51604 voutp2p_waveforma_slusba6.png
VIN = 7.2 V IOUT = 12 A
Figure 22. Output Ripple