SLUSBA6B December 2012 – October 2015 TPS51604
The TPS51604 device is a synchronous-buck MOSFET driver designed to drive both high-side and low-side MOSFETs. It allows high-frequency operation with current driving capability matched to the application. The integrated boost switch is internal. The TPS51604 device employs dead-time reduction control and shoot-through protection, which helps avoid simultaneous conduction of high-side and low-side MOSFETs. Also, the drivers improve light-load efficiency with integrated DCM-mode operation using adaptive crossing detection. Typical applications yield a steady-state duty cycle of 60% or less. For high steady-state duty cycle applications, including a small external Schottky diode may help to ensure sufficient charging of the bootstrap capacitor.
The UVLO comparator evaluates the VDD voltage level. As VVDD rises, both DRVH and DRVL hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H). Then, the driver becomes operational and responds to PWM and SKIP commands. If VDD falls below the lower UVLO threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of DRVH and DRVL actively low. Figure 15 shows this function.
Do not start the driver in the very low power mode (SKIP = Tri-state).
The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin incorporates a weak pullup to maintain the voltage within the tri-state window during low-power modes. Operation into and out of a tri-state condition follows the timing diagram outlined in Figure 16.
When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The window is defined as the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3-V (typical) and 5-V (typical) PWM drive signals.
When the PWM exits the tri-state condition, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP pin. Typical operation requires this time period in order for the auto-zero comparator to resume.
The SKIP pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP is low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current is less than the critical current. When SKIP is high, the ZX comparator disables, and the converter enters FCCM mode. When the SKIP pin is in a tri-state condition, typical operation forces the gate driver outputs low and the driver enters a very-low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent current. When the SKIP pin voltage is pulled either low or high, the driver wakes up and is able to accept PWM pulses in less than 50 µs.
Table 1 shows the logic functions of UVLO, PWM, SKIP, DRVH, and DRVL.
|Inactive||High||H or L||Low||High|
|Inactive||Tri-state||H or L||Low||Low||Low power|
The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the rectifying MOSFET.
The driver utilizes an anti-shoot-through and adaptive dead-time control to minimize low-side body diode conduction time and maintain high efficiency. When the PWM input voltage becomes high, the low-side MOSFET gate voltage begins to fall after a propagation delay. At the same time, DRVL voltage is sensed, and high-side driving voltage starts to increase after DRVL voltage is lower than a proper threshold.
Typical operation manages to near zero the dead-time between the low-side gate turn-off to high-side gate voltage turn-on, and high-side gate turn-off to low-side gate turn-on, in order to avoid simultaneous conduction of both MOSFETs, as well as to reduce body diode conduction and recovery losses. This operation also reduces ringing on the leading edge of the SW waveform.
To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the conventional diode between the VDD pin and BST pin is replaced by a FET, which is gated by the DRVL signal.
The TPS51604 device operates in CCM mode when the SKIP pin is high, and it enters DCM mode when the SKIP pin is low. When both the SKIP pin and the PWM pin are in a tri-state condition, it forces the gate driver outputs low and the driver enters a very-low-power state.