JAJSIO3A February   2020  – September 2020 TPS546B24A

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Average Current-Mode Control
        1. 7.3.1.1 On-Time Modulator
        2. 7.3.1.2 Current Error Integrator
        3. 7.3.1.3 Voltage Error Integrator
      2. 7.3.2  Linear Regulators
      3. 7.3.3  AVIN and PVIN Pins
      4. 7.3.4  Input Undervoltage Lockout (UVLO)
        1. 7.3.4.1 Fixed AVIN UVLO
        2. 7.3.4.2 Fixed VDD5 UVLO
        3. 7.3.4.3 Programmable PVIN UVLO
        4. 7.3.4.4 EN/UVLO Pin
      5. 7.3.5  Start-Up and Shutdown
      6. 7.3.6  Differential Sense Amplifier and Feedback Divider
      7. 7.3.7  Set Output Voltage and Adaptive Voltage Scaling (AVS)
        1. 7.3.7.1 Reset Output Voltage
        2. 7.3.7.2 Soft Start
      8. 7.3.8  Prebiased Output Start-Up
      9. 7.3.9  Soft Stop and (65h) TOFF_FALL Command
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Set Switching Frequency
      12. 7.3.12 Frequency Synchronization
      13. 7.3.13 Loop Slave Detection
      14. 7.3.14 Current Sensing and Sharing
      15. 7.3.15 Telemetry
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Overvoltage/Undervoltage Protection
      18. 7.3.18 Overtemperature Management
      19. 7.3.19 Fault Management
      20. 7.3.20 Back-Channel communication
      21. 7.3.21 Switching Node (SW)
      22. 7.3.22 PMBus General Description
      23. 7.3.23 PMBus Address
      24. 7.3.24 PMBus Connections
    4. 7.4 Device Functional Modes
      1. 7.4.1 Programming Mode
      2. 7.4.2 StandAlone/Master/Slave Mode Pin Connections
      3. 7.4.3 Continuous Conduction Mode
      4. 7.4.4 Operation With CNTL Signal (EN/UVLO)
      5. 7.4.5 Operation with Control
      6. 7.4.6 Operation with CNTL and Control
    5. 7.5 Programming
      1. 7.5.1 Supported PMBus Commands
      2. 7.5.2 Pin Strapping
        1. 7.5.2.1 Programming MSEL1
        2. 7.5.2.2 Programming MSEL2
        3. 7.5.2.3 Programming VSEL
        4. 7.5.2.4 Programming ADRSEL
        5. 7.5.2.5 Programming MSEL2 for a Slave Device (GOSNS Tied to BP1V5)
        6. 7.5.2.6 Pin-Strapping Resistor Configuration
    6. 7.6 Register Maps
      1. 7.6.1  Conventions for Documenting Block Commands
      2. 7.6.2  (01h) OPERATION
      3. 7.6.3  (02h) ON_OFF_CONFIG
      4. 7.6.4  (03h) CLEAR_FAULTS
      5. 7.6.5  (04h) PHASE
      6. 7.6.6  (10h) WRITE_PROTECT
      7. 7.6.7  (15h) STORE_USER_ALL
      8. 7.6.8  (16h) RESTORE_USER_ALL
      9. 7.6.9  (19h) CAPABILITY
      10. 7.6.10 (1Bh) SMBALERT_MASK
      11. 7.6.11 (1Bh) SMBALERT_MASK_VOUT
      12. 7.6.12 (1Bh) SMBALERT_MASK_IOUT
      13. 7.6.13 (1Bh) SMBALERT_MASK_INPUT
      14. 7.6.14 (1Bh) SMBALERT_MASK_TEMPERATURE
      15. 7.6.15 (1Bh) SMBALERT_MASK_CML
      16. 7.6.16 (1Bh) SMBALERT_MASK_OTHER
      17. 7.6.17 (1Bh) SMBALERT_MASK_MFR
      18. 7.6.18 (20h) VOUT_MODE
      19. 7.6.19 (21h) VOUT_COMMAND
      20. 7.6.20 (22h) VOUT_TRIM
      21. 7.6.21 (24h) VOUT_MAX
      22. 7.6.22 (25h) VOUT_MARGIN_HIGH
      23. 7.6.23 (26h) VOUT_MARGIN_LOW
      24. 7.6.24 (27h) VOUT_TRANSITION_RATE
      25. 7.6.25 (29h) VOUT_SCALE_LOOP
      26. 7.6.26 (2Bh) VOUT_MIN
      27. 7.6.27 (33h) FREQUENCY_SWITCH
      28. 7.6.28 (35h) VIN_ON
      29. 7.6.29 (36h) VIN_OFF
      30. 7.6.30 (37h) INTERLEAVE
      31. 7.6.31 (38h) IOUT_CAL_GAIN
      32. 7.6.32 (39h) IOUT_CAL_OFFSET
      33. 7.6.33 (40h) VOUT_OV_FAULT_LIMIT
      34. 7.6.34 (41h) VOUT_OV_FAULT_RESPONSE
      35. 7.6.35 (42h) VOUT_OV_WARN_LIMIT
      36. 7.6.36 (43h) VOUT_UV_WARN_LIMIT
      37. 7.6.37 (44h) VOUT_UV_FAULT_LIMIT
      38. 7.6.38 (45h) VOUT_UV_FAULT_RESPONSE
      39. 7.6.39 (46h) IOUT_OC_FAULT_LIMIT
      40. 7.6.40 (47h) IOUT_OC_FAULT_RESPONSE
      41. 7.6.41 (4Ah) IOUT_OC_WARN_LIMIT
      42. 7.6.42 (4Fh) OT_FAULT_LIMIT
      43. 7.6.43 (50h) OT_FAULT_RESPONSE
      44. 7.6.44 (51h) OT_WARN_LIMIT
      45. 7.6.45 (55h) VIN_OV_FAULT_LIMIT
      46. 7.6.46 (56h) VIN_OV_FAULT_RESPONSE
      47. 7.6.47 (58h) VIN_UV_WARN_LIMIT
      48. 7.6.48 (60h) TON_DELAY
      49. 7.6.49 (61h) TON_RISE
      50. 7.6.50 (62h) TON_MAX_FAULT_LIMIT
      51. 7.6.51 (63h) TON_MAX_FAULT_RESPONSE
      52. 7.6.52 (64h) TOFF_DELAY
      53. 7.6.53 (65h) TOFF_FALL
      54. 7.6.54 (78h) STATUS_BYTE
      55. 7.6.55 (79h) STATUS_WORD
      56. 7.6.56 (7Ah) STATUS_VOUT
      57. 7.6.57 (7Bh) STATUS_IOUT
      58. 7.6.58 (7Ch) STATUS_INPUT
      59. 7.6.59 (7Dh) STATUS_TEMPERATURE
      60. 7.6.60 (7Eh) STATUS_CML
      61. 7.6.61 (7Fh) STATUS_OTHER
      62. 7.6.62 (80h) STATUS_MFR_SPECIFIC
      63. 7.6.63 (88h) READ_VIN
      64. 7.6.64 (8Bh) READ_VOUT
      65. 7.6.65 (8Ch) READ_IOUT
      66. 7.6.66 (8Dh) READ_TEMPERATURE_1
      67. 7.6.67 (98h) PMBUS_REVISION
      68. 7.6.68 (99h) MFR_ID
      69. 7.6.69 (9Ah) MFR_MODEL
      70. 7.6.70 (9Bh) MFR_REVISION
      71. 7.6.71 (9Eh) MFR_SERIAL
      72. 7.6.72 (ADh) IC_DEVICE_ID
      73. 7.6.73 (AEh) IC_DEVICE_REV
      74. 7.6.74 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
      75. 7.6.75 (B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
      76. 7.6.76 (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
      77. 7.6.77 (DAh) MFR_SPECIFIC_10 (READ_ALL)
      78. 7.6.78 (DBh) MFR_SPECIFIC_11 (STATUS_ALL)
      79. 7.6.79 (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
      80. 7.6.80 (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG)
      81. 7.6.81 (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
      82. 7.6.82 (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
      83. 7.6.83 (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
      84. 7.6.84 (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
      85. 7.6.85 (EFh) MFR_SPECIFIC_31 (SLAVE_ADDRESS)
      86. 7.6.86 (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
      87. 7.6.87 (F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
      88. 7.6.88 (FCh) MFR_SPECIFIC_44 (FUSION_ID0)
      89. 7.6.89 (FDh) MFR_SPECIFIC_45 (FUSION_ID1)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
          1. 8.2.2.4.1 Output Voltage Deviation During Load Transient
          2. 8.2.2.4.2 Output Voltage Ripple
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  AVIN, BP1V5, VDD5 Bypass Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  R-C Snubber
        9. 8.2.2.9  Output Voltage Setting (VSEL Pin)
        10. 8.2.2.10 Compensation Selection (MSEL1 Pin)
        11. 8.2.2.11 Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
        12. 8.2.2.12 Enable and UVLO
        13. 8.2.2.13 ADRSEL
        14. 8.2.2.14 Pin-Strapping Resistor Selection
        15. 8.2.2.15 BCX_CLK and BCX_DAT
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Texas Instruments Fusion Digital Power Designer
        2. 11.1.2.2 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VAVIN Input supply voltage range 2.95 16 V
VPVIN Power stage voltage range 2.95 16
IAVIN Input operating current Converter not switching 12.5 17 mA
AVIN UVLO
VAVINuvlo Analog input voltage UVLO for power on reset (PMBus communication) enable threshold 2.5 2.7 V
Analog input voltage UVLO for disable 2.09 2.3 V
Analog input voltage UVLO hysteresis 250 mV
tdelay(uvlo_PMBus) Delay from AVIN UVLO to PMBus ready to communicate AVIN = 3 V 10 ms
PVIN UVLO
VIN_ON Power input turn on voltage Factory default setting 2.75 V
Programmable range 2.75 15.75
Resolution 0.25
Accuracy  –5% 5%
VIN_OFF Power input turnoff voltage Factory default setting 2.5 V
Programmable range 2.5 15.5
Resolution 0.25
Accuracy  –5% 5%
ENABLE AND UVLO
VENuvlo EN/UVLO Voltage rising threshold 1.05 1.1 V
EN/UVLO Voltage falling threshold 0.9
VENhys EN/UVLO Voltage hysteresis No external resistors on EN/UVLO 70 mV
IENhys EN/UVLO hysteresis current VEN/UVLO = 1.1 V 4.5 5.5 6.5 uA
EN/UVLO hysteresis current VEN/UVLO = 0.9 V -100 -5 nA
REMOTE SENSE AMPLIFIER
ZRSA Remote sense input impedance VOSNS  – GOSNS = 1V VOSNS to GOSNS 85 130 165
VIRNG(GOSNS) GOSNS input range for regulation accuracy (1) VOSNS  – GOSNS = 1V, VOUT_SCALE_LOOP ≤ 0.5  –0.05 0.05 V
VIRNG(VOSNS) VOSNS input range for regulation accuracy (1) GOSNS = AGND, VOUT_SCALE_LOOP ≤ 0.5  –0.1 5.5 V
REFERENCE VOLTAGE AND ERROR AMPLIFIER
VREF Reference voltage(1) Default setting 0.4 V
Reference voltage range(1) 0.25 0.75 V
Reference voltage resolution(1) 2 –12 V
VOUT(ACC) Output voltage accuracy VOUT = 1000 mV  –40°C ≤ TJ ≤ 150°C(2) 0.992 1.008 V
VOUT = 500 mV 0.492 0.508 V
VOUT = 1500 mV 1.490 1.510 V
VOUT = 1000 mV  0°C ≤ TJ ≤ 125°C(2) 0.994 1.006 V
VOUT = 500 mV 0.494 0.506 V
VOUT = 1500 mV 1.492 1.508 V
VOUT = 1000 mV 0°C ≤ TJ ≤ 85°C(2) 0.995 1.005 V
VOUT = 500 mV 0.495 0.505 V
VOUT = 1500 mV 1.493 1.507 V
GmEA Progrmmable error amplifier transonductance 25 200 µS
Resolution(1) Four settings: 25 uS, 50 uS, 100 uS, 200 uS 25
Unloaded Bandwidth(1) 8 MHz
RpEA Programmable parallel resistor range 5 315 kΩ
Resolution(1) 5
CintEA Programmable integrator capacitor range 1.25 18.75 pF
Resolution(1) 1.25 pF
CpEA Programmable parallel capacitor range 6.25 193.75 pF
Resolution(1) 6.25
CURRENT GM AMPLIFIER
GmBUF Progrmmable current error amplifier transonductance 25 200 µS
Resolution(1) Four settings: 25 µS, 50 µS, 100 µS, 200 µS 25
Unloaded bandwidth(1) 17 MHz
RpBUF Programmable parallel resistor range 5 315 kΩ
Resolution(1) 5
RintBUF Programmable integrator resistor range(1) 800 1600 kΩ
Resolution(1) 800
CintBUF Programmable integrator capacitor range 0.3125 4.6875 pF
Resolution(1) 0.3125
CpBUF Programmable parallel capacitor range 3.125 96.875 pF
Resolution(1) 3.125
OSCILLATOR
fSW Adjustment range(2) 225 1500 kHz
Switching frequency(2) 500 550 600
SYNCHRONIZATION
VIH(sync) High-level input voltage 1.35 V
VIL(sync) Low-level input voltage 0.8
tpw(sync) Sync input minimum pulse width fsw = 225 kHz to 1500 kHz 200 ns
ΔfSYNC SYNC pin frequency range from FREQUENCY_SWITCH frequency(1)  –20 20 %
VOH(sync) Sync output high voltage 100-μA load VDD5  –0.85V VDD5 V
VOL(sync) Sync output low voltage 2.4-mA load 0.4 V
tPLL PLL lock time Fsw = 550 kHz, SYNC clock frequency 495 kHz - 605 kHz(1) 65 μs
PhaseErr Phase interleaving error(5) fsw < 1.1 MHz 9 Degree
fsw ≥1.1 MHz 23 ns
RESET
VIH(reset) High-level input voltage(1) 1.35 V
VIL(reset) Low-level input voltage 0.8
tpw(reset) Minimum RESET_B pulse width 200 ns
Rpullup(reset) Internal pull-up resistance VRESET = 0.8V RESET# = 1 25 34 55
Vpullup(reset) Internal Pull-up Voltage IRESET = 10 μA RESET# = 1 VDD5 - 0.5 V
VDD5 REGULATOR
VVDD5 Regulator output voltage Default, IVDD5 = 10 mA 4.5 4.7 4.9 V
Programmable range(1) 3.9 5.3 V
Resolution 200 mV
VVDD5(do) Regulator dropout voltage VAVIN  – VVDD5, VAVIN = 4.5 V, IVDD5 = 25 mA 130 285 mV
VVDD5ON(IF) Enable voltage on VDD5 for pin-strapping 2.62 2.85 V
VVDD5OFF(IF) Disable voltage on VDD5 for pin-strapping 2.25 2.48 V
VVDD5ON(SW) Switching enable voltage upon VDD5 4.05 V
VVDD5OFF(SW) Switching disable voltage upon VDD5 3.10 V
VVDD5UV(hyst) Regulator UVLO voltage hysteresis 400 mV
BOOTSTRAP
VBOOT(drop) Bootstrap voltage drop IBOOT = 20 mA, VDD5 = 4.5 V 225 mV
BP1V5 REGULATOR
VBP1V5 1.5-V regulator output voltage VAVIN ≥ 4.5 V, IBP1V5 = 5 mA 1.42 1.5 1.58 V
IBP1V5SC 1.5-V regulator short-circuit current(1) 30 mA
PWM
tON(min) Minimum controllable pulse width(1) 20 ns
tOFF(min) PWM Minimum off-time(1) 400 500 ns
SOFT START
tON_RISE Soft-start time Factory default setting 3 ms
Programmable range(1) (3) 0 31.75
Resolution 0.25
Accuracy, TON_RISE = 3 ms  –10% 15%
tON_MAX_FLT_LT Upper limit on the time to power up the output Factory default setting(4) 0 ms
Programmable range(1) (4) 0 127.5
Resolution 0.5
Accuracy(1)  –10% 15%
tON_DELAY Turn-on delay Factory default setting 0 ms
Programmable range(1) 0 127.5
Resolution 0.5
Accuracy(1)  –10% 15%
SOFT STOP
tOFF_FALL Soft-stop time Factory default setting(3) 0.5 ms
Programmable range (1) (3) 0 31.75
Resolution 0.25
Accuracy, TOFF_FALL = 1 ms  –10% 15%
tOFF_DELAY Turn-off delay Factory default setting 0 ms
Programmable range(1) 0 127.5
Resolution 0.5
Accuracy(1)  –10% 15%
VPVINOVF Power Input overvoltage fault limit Factory default 21 V
Programmable range 6 20
Resolution 1
VPVINUVW Power Input undervoltage warning limit Factory default 2.5 V
Programmable range 5 15.75
Resolution 0.25
POWER STAGE
RHS High-side power device on-resistance VBOOT - VSW = 4.5V, TJ = 25°C 5.5
VBOOT - VSW = 3 V, TJ = 25°C 8.5
RLS Low-side power device on-resistance VVDD5 = 4.5 V, TJ = 25°C 1.8
VVDD5 = 3 V, TJ = 25°C 3.0
Rswpd SW internal pull-down resistance 3 30 35 kΩ
Vwkdr(on) Weak high-side gate drive triggering threshold upon PVIN rising 14.75 V
Vwkdr(off) Weak high-side gate drive recovering threshold upon PVIN falling 14.35 V
tDEAD(LtoH) Power stage driver dead-time from Low-side off to High-side on VVDD5 = 4.5 V, TJ = 25°C(1) 6 ns
tDEAD(HtoL) Power stage driver dead-time from High-side off to Low-side on VVDD5 = 4.5 V, TJ = 25°C(1) 6 ns
CURRENT SHARING
ISHARE(acc) Output current sharing accuracy of two devices defined as the ratio of the current difference between two devices to the sum of the two IOUT ≥ 10 A per device(5)  –10% 10%
Output current sharing accuracy of two devices defined as the current difference between each device and the average of all devices IOUT < 10 A per device(5)  –1 1 A
ISHARE(ratio) Current Share Ratio between TPS546B24A and TPS546D24A IOUT(B24A + D24A) = 30A(5) 0.5
VVSHARE VSHARE fault trip threshold 0.1 V
VSHARE fault release threshold 0.2
LOW-SIDE CURRENT LIMIT PROTECTION
tOFF(OC) Off time between restart attempts(1) Factory default setting 7 × tON_RISE ms
Range 1 × tON_RISE 7 × tON_RISE
IO_OC_FLT_LMT Output current overcurrent fault threshold Factory default setting 26 A
Programmable range 4 31
Resolution 1
INEGOC Negative output current overcurrent protection threshold  –10
IO_OC_WRN_LMT Output current overcurrent warning threshold Factory default setting 20 A
Programmable range 4 31
Resolution 1
IHSOC Output current overcurrent fault accuracy IOUT = 10 A  –1 2 A
IOUT = 20 A(5)  –2 4
HIGH-SIDE SHORT CIRCUIT PROTECTION
IHSOC Ratio of High-side short-circuit protection fault threshold over Low-side overcurrent limit (VBOOT  – VSW) = 4.5V, TJ = 25°C(5) 105% 150% 200%
High-side current sense blanking time 100 ns
POWER GOOD (PGOOD) AND OVERVOLTAGE/UNDERVOLTAGE WARNING
RPGD PGD pulldown resistance IPGD = 5 mA 30 50 Ω
IPGD(OH) Output high open drain leakage current into PGD pin VPGD = 5 V 15 µA
VPGD(OL) PGD pin output low level voltage at no supply voltage VAVIN = 0, IPGD = 80 μA 0.8 V
VOVW Overvoltage warning threshold (PGD threshold on VOSNS rising) Factory default, at VOUT_COMMAND (VOC) = 1 V 106% 110% 114% VOC
Range 103% 116%
Resolution 1%
VUVW Undervoltage warning threshold (PGD threshold on VOSNS falling) Factory default, at VOUT_COMMAND (VOC) = 1 V 86% 90% 94%
Range 84% 97%
Resolution 1%
VPGD(rise) PGD release threshold on VOSNS rising and undervoltage warning de-assertion threshold Factory default, at VOUT_COMMAND (VOC) = 1 V 95%
VPGD(fall) PGD threshold on VOSNS falling and overvoltage warning de-assertion threshold Factory default, at VOUT_COMMAND (VOC) = 1 V 105%
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE FAULT PROTECTION
VOVF Overvoltage fault threshold Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND (VOC) = 1 V 111% 115% 119% VOC
Range Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND (VOC) = 1 V 105% 140%
Resolution Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND (VOC) = 1 V 2.5%
VUVF Undervoltage fault threshold Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND = 1.00 V 81% 85% 89%
Range Factory default, at VOUT_COMMAND = 1.00 V Factory default, at VOUT_COMMAND = 1.00 V 60% 95%
Resolution Factory default, at VOUT_COMMAND = 1.00 V Factory default, at VOUT_COMMAND = 1.00 V 2.5%
VOVF(fix)OFF Fixed overvoltage fault threshold Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND = 1.00 V 1.15 1.2 1.25 V
Recovery threshold(1) Factory default, at VOUT_COMMAND = 1.00 V Factory default, at VOUT_COMMAND = 1.00 V 0.4
OUTPUT VOLTAGE TRIMMING
VOUTRES Default Resolution of VOUT_COMMAND, Trim and Margin, VOUT_SCALE_LOOP = 0.5 1.90 1.95 2.00 mV
Programmable range(1) 2–12 2 –5 V
VOUT_TRAN_RT Output voltage transition rate Factory default setting 1 mV/µs
Programmable range(1) 0.063 15.933
Accuracy  –10% 10%
VOUT_SCL_LP Feedback loop scaling factor(1) Factory default setting 0.5
Programmable range, 4 discrete settings 0.125 1
VOUT_CMD Output voltage programmable values Factory default setting 0.8 V
Programmable range VOUT_SCALE_LOOP = 1 (5) 0.25 0.75 V
VOUT_SCALE_LOOP = 0.5 0.25 1.5
VOUT_SCALE_LOOP = 0.25(5) 0.25 3
VOUT_SCALE_LOOP = 0.125(5) 0.25 6
TEMPERATURE SENSE AND THERMAL SHUTDOWN
TSD Bandgap thermal shutdown temperature(1) 150 170 °C
THYST Bandgap thermal shutdown hysteresis(1) 25
OT_FLT_LMT Internal overtemperature fault limit(1) Factory default setting 150
Programmable range 0 160
Resolution 1
OT_WRN_LMT Internal overtemperature warning limit(1) Factory default setting 125
Programmable range 0 160
Resolution 1
TOT(hys) Internal overtemperature fault, warning hysteresis(1) Factory default setting 25
MEASUREMENT SYSTEM
MVOUT(rng) Output voltage measurement range(1) 0 6 V
MVOUT(acc) Output voltage measurement accuracy 250 mV < VOUT < 6 V  –2% 2%
MVOUT(lsb) Output voltage measurement bit resolution(1) 244 µV
MIOUT(rng) Output current measurement range(1)  –5 30 A
MIOUT(acc) Output current measurement accuracy(5) IOUT ≤ 5 A, TJ = 25°C  –1 0 1 A
MIOUT(acc) Output current measurement accuracy(5) IOUT = 10A, -40°C ≤ TJ ≤ 150°C  –1.5 0 1.5 A
MIOUT(acc) Output current measurement accuracy(5) IOUT = 20A, -40°C ≤ TJ ≤ 150°C  –2 0 2 A
MIOUT(acc) Output current measurement accuracy(5) IOUT = 10A, 0°C ≤ TJ ≤ 85°C  –1.3 0 1.3 A
MIOUT(acc) Output current measurement accuracy(5) IOUT = 20A, 0°C ≤ TJ ≤ 85°C  –1.5 0 1.5 A
MIOUT(lsb) Output current measurement bit resolution(1) 2–6 A
MPVIN(rng) Input voltage measurement range(1) 0 20 V
MPVIN(acc) Input voltage measurement accuracy 4 V< PVIN < 20 V  –3 3 %
MPVIN(lsb) Input voltage measurement bit resolution(1) 2–6 V
MTSNS(acc) Internal temperature sense accuracy(5) –40°C ≤ TJ ≤ 150°C  –3 3 °C
MTSNS(lsb) Internal temperature sense bit resolution(1) 0.25
PMBUS INTERFACE + BCX
VIH(PMBUS) High-level input voltage on PMB_CLK, PMB_DATA, BCX_CLK, BCX_DAT 1.35 V
VIL(PMBUS) Low-level input voltage on PMB_CLK, PMB_DATA, BCX_CLK, BCX_DAT 0.8
IlH(PMBUS) Input high level current into PMB_CLK, PMB_DATA  –10 10 μA
IIL(PMBUS) Input low level current into PMB_CLK, PMB_DATA  –10 10 μA
VOL(PMBUS) Output low level votlage on PMB_DATA, SMB_ALRT, BCX_DAT VAVIN > 4.5 V, input current to PMB_DATA, SMB_ALRT, BCX_DAT = 20 mA 0.4 V
IOH(PMBUS) Output high level open drain leakage current into PMB_DATA, SMB_ALRT Voltage on PMB_DATA, SMB_ALRT = 5.5 V 10 μA
IOL(PMBUS) Output low level open drain sinking current on PMB_DATA, SMB_ALRT, BCX_DAT Voltage on PMB_DATA, SMB_ALRT, BCX_DAT = 0.4 V 20 mA
fPMBUS_CLK PMBus operating frequency range GOSNS = AGND 10 1000 kHz
CPMBUS PMBUS_CLK & PMBUS_DATA pin input capactiance(1) Vpin = 0.1V to 1.35V 5 pF
NWR_NVM Number of NVM writeable cycles(1)  –40°C to 150°C 1000 cycle
tCLK_STCH(max) Maximum Allowable Clock Stretch(1) 6 ms
Specified by design. Not production tested.
The parameter covers 2.95 V to 18 V of AVIN.
The setting of TON_RISE and TOFF_FALL of 0 ms means the unit to bring its output voltage to the programmed regulation value of down to 0 as quickly as possible, which results in an effective TON_RISE and TOFF_FALL time of 0.5 ms (fastest time supported).
The setting of TON_MAX_FAULT_LIMIT and TOFF_MAX_WARN_LIMIT of 0 means disabling TON_MAX_FAULT and TOFF_MAX_WARN response and reporting completely.
Not production tested. Guaranteed by correlation.  AVIN = PVIN = 12 V, VOUT = 1 V fsw = 325kHz L = 320nH