JAJSE66E
June 2017 – December 2022
TPS650864
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics: Total Current Consumption
7.6
Electrical Characteristics: Reference and Monitoring System
7.7
Electrical Characteristics: Buck Controllers
7.8
Electrical Characteristics: Synchronous Buck Converters
7.9
Electrical Characteristics: LDOs
7.10
Electrical Characteristics: Load Switches
7.11
Digital Signals: I2C Interface
7.12
Digital Input Signals (CTLx)
7.13
Digital Output Signals (IRQB, GPOx)
7.14
Timing Requirements
7.15
Switching Characteristics
7.16
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
TPS6508640 Design and Settings
8.3.1
TPS6508640 OTP Summary
8.4
TPS65086401 Design and Settings
8.4.1
TPS65086401 OTP Summary
31
8.5
TPS6508641 Design and Settings
8.5.1
TPS6508641 OTP Summary
8.6
TPS65086470 Design and Settings
8.6.1
TPS65086470 OTP Summary
8.7
SMPS Voltage Regulators
8.7.1
Controller Overview
8.7.2
Converter Overview
8.7.3
DVS
8.7.4
Decay
8.7.5
Current Limit
8.8
LDOs and Load Switches
8.8.1
VTT LDO
8.8.2
LDOA1–LDOA3
8.8.3
Load Switches
8.9
Power Goods (PGOOD or PG) and GPOs
8.10
Power Sequencing and VR Control
8.10.1
CTLx Sequencing
8.10.2
PG Sequencing
8.10.3
Enable Delay
8.10.4
Power-Up Sequence
8.10.5
Power-Down Sequence
8.10.6
Sleep State Entry and Exit
8.10.7
Emergency Shutdown
8.11
Device Functional Modes
8.11.1
Off Mode
8.11.2
Standby Mode
8.11.3
Active Mode
8.12
I2C Interface
8.12.1
F/S-Mode Protocol
8.13
Register Maps
8.13.1
Register Map Summary
8.13.2
DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
8.13.3
DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
8.13.4
IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
8.13.5
IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
8.13.6
PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
8.13.7
SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
8.13.8
BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
8.13.9
BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
8.13.10
BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
8.13.11
BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
8.13.12
BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
8.13.13
BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
8.13.14
BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
8.13.15
BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
8.13.16
LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
8.13.17
LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
8.13.18
DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
8.13.19
DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
8.13.20
DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
8.13.21
PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
8.13.22
FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
8.13.23
BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
8.13.24
BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
8.13.25
BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
8.13.26
BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
8.13.27
BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
8.13.28
BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
8.13.29
BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
8.13.30
BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
8.13.31
LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
8.13.32
LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
8.13.33
BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
8.13.34
PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
8.13.35
SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
8.13.36
I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
8.13.37
I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h) [reset = X]
8.13.38
PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
8.13.39
PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
8.13.40
GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
8.13.41
GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
8.13.42
GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
8.13.43
GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
8.13.44
GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
8.13.45
GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
8.13.46
GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
8.13.47
GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
8.13.48
MISCSYSPG Register (offset = ACh) [reset = X]
8.13.48.1
VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
8.13.49
LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
8.13.50
PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
8.13.51
PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
8.13.52
PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]
8.13.53
PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]
8.13.54
TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
8.13.55
TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
8.13.56
OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
9
Applications, Implementation, and Layout
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Controller Design Procedure
9.2.2.1.1
Selecting the Inductor
9.2.2.1.2
Selecting the Output Capacitors
9.2.2.1.3
Selecting the FETs
9.2.2.1.4
Bootstrap Capacitor
9.2.2.1.5
Setting the Current Limit
9.2.2.1.6
Selecting the Input Capacitors
9.2.2.2
Converter Design Procedure
9.2.2.2.1
Selecting the Inductor
9.2.2.2.2
Selecting the Output Capacitors
9.2.2.2.3
Selecting the Input Capacitors
9.2.2.3
LDO Design Procedure
9.2.3
Application Curves
9.2.4
Layout
9.2.4.1
Layout Guidelines
9.2.4.2
Layout Example
9.2.5
VIN 5-V Application
9.2.5.1
Design Requirements
9.2.5.2
Design Procedure
9.2.5.3
Application Curves
9.3
Power Supply Coupling and Bulk Capacitors
9.4
Do's and Don'ts
10
Device and Documentation Support
10.1
Device Support
10.1.1
Third-Party Products Disclaimer
10.1.2
Development Support
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
サポート・リソース
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RSK|64
MPQF192B
サーマルパッド・メカニカル・データ
RSK|64
QFND521
発注情報
jajse66e_oa
jajse66e_pm
1
特長
5.6V~21V の広い V
IN
範囲
D-CAP2™
トポロジを採用した 3 つの可変出力電圧同期整流
降圧型コントローラ
外付けの FET を使用して出力電流をスケーリング可能、電流制限を選択可能
I
2
C により、0.41V~1.67V の範囲で 10mV 刻み、
または 1V~3.575V の範囲で 25mV 刻みの DVS 制御が可能
DCS-Control トポロジを採用した 3 つの可変出力電圧同期整流降圧型コンバータ
V
IN
範囲は
3V
~5.5V
最大 3A の出力電流
I
2
C により、0.41V~1.67V の範囲で 10mV 刻み、
または 0.425V~3.575V の範囲で 25mV 刻みの DVS 制御が可能
出力電圧可変の 3 つの LDO レギュレータ
LDOA1:I
2
C により電圧を 1.35V~3.3V の範囲で選択可能、最大出力電流 200mA
LDOA2 および LDOA3:I
2
C により電圧を 0.7V~1.5V の範囲で選択可能、最大出力電流 600mA
DDR
メモリ終端用の VTT LDO
スルー・レート制御付きの 3 つの負荷スイッチ
最大 300mA の出力電流、電圧降下は公称入力電圧の 1.5% 未満
入力電圧 1.8V において R
DSON
< 96mΩ
5V 固定出力電圧の LDO (LDO5)
SMPS のゲート・ドライバおよび LDOA1 用の電源
外部 5V 降圧への自動切り替えにより高効率を実現
工場での
OTP プログラミングにより柔軟な構成が可能
6 つの GPI ピンを、選択した任意のレールのイネーブル (CTL1~CTL6) またはスリープ・モード移行 (CTL3 および CTL6) に構成可能
4 つの GPO ピンを、選択した任意のレールのパワー・グッドに構成可能
オープン・ドレインの割り込み出力ピン
I
2
C インターフェイスにより Standard Mode (100kHz)、Fast Mode (400kHz)、Fast Mode Plus (1MHz) をサポート