SLVSC70A January   2015  – January 2015 TPS65251-1 , TPS65251-2 , TPS65251-3

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics for Buck 1
    7. 6.7 Typical Characteristics for Buck 2
    8. 6.8 Typical Characteristics for Buck 3
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjustable Switching Frequency
      2. 7.3.2  Synchronization
      3. 7.3.3  Out-of-Phase Operation
      4. 7.3.4  Delayed Start-Up
      5. 7.3.5  Soft-Start Time
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Input Capacitor
      8. 7.3.8  Bootstrap Capacitor
      9. 7.3.9  Error Amplifier
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power Good
      12. 7.3.12 3.3-V and 6.5-V LDO Regulators
      13. 7.3.13 Current Limit Protection
      14. 7.3.14 Overvoltage Transient Protection (OVP)
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Power/Pulse Skipping Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Loop Compensation Circuit
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Soft-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Adjustable Current Limiting Resistor Selection
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 3.3-V and 6.5-V LDO Regulators
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device is triple synchronous step down dc/dc converter. It is typically used to convert a higher dc voltage to lower dc voltages with continuous available output current of 3 A/2 A/2 A. The following design procedure can be used to select component values for the TPS65251-x.

8.2 Typical Application

typ_app_lvsc70.gif
A. VIN pins require local decoupling capacitors.
Figure 23. Typical Application Circuit

8.2.1 Design Requirements

DESIGN PARAMETERS VALUE
Output voltage 1.2 V
Transient response 0.5-A to 2-A load step 120 mV
Maximum output current 3 A
Input voltage 12 V nom, 9.6 to 14.4 V
Output voltage ripple <30 mV p-p
Switching frequency 500 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Loop Compensation Circuit

A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60° and 90°, or type III (Rc, Cc and Cff) to improve the converter transient response. CRoll adds a high frequency pole to attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there is possibility of cross coupling in between rails when layout is very compact.

loop_comp1_lvsaa4.gifFigure 24. Loop Compensation

To calculate the external compensation components use Table 1:

Table 1. Design Guideline for the Loop Compensation

TYPE II CIRCUIT TYPE III CIRCUIT
Select switching frequency that is appropriate for application depending on L, C sizes, output ripple, EMI concerns and etc. Switching frequencies between 500 kHz and 1 MHz give best trade off between performance and cost. When using smaller L and Cs, switching frequency can be increased. To optimize efficiency, switching frequency can be lowered. Type III circuit recommended for switching frequencies higher than 500 kHz.
Select cross over frequency (fc) to be less than 1/5 to 1/10 of switching frequency. Suggested
fc = fs/10
Suggested
fc = fs/10
Set and calculate Rc.
Equation 6. eq6_rc_lvsaa4.gif
Equation 7. eq6a_rc_lvsaa4.gif
Calculate Cc by placing a compensation zero at or before the converter dominant pole
Equation 8. eq7a_fp_lvsaa4.gif
Equation 9. eq7_cc_lvsaa4.gif
Equation 10. eq7_cc_lvsaa4.gif
Add CRoll if needed to remove large signal coupling to high impedance COMP node. Make sure that
Equation 11. eq8_fproll_lvsaa4.gif
is at least twice the cross over frequency.
Equation 12. eq9_croll_lvsaa4.gif
Equation 13. eq9_croll_lvsaa4.gif
Calculate Cff compensation zero at low frequency to boost the phase margin at the crossover frequency. Make sure that the zero frequency (fzff is smaller than soft-start equivalent frequency (1/Tss). NA
Equation 14. eq10_cff_lvsaa4.gif

8.2.2.2 Selecting the Switching Frequency

The first step is to decide on a switching frequency for the regulator. Typically, you will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter’s performance. The converter is capable of running from 300 kHz to 2.2 MHz. Unless a small solution size is an ultimate goal, a moderate switching frequency of 500 kHz is selected to achieve both a small solution size and a high efficiency operation. Using Figure 19, R1 is determined to be 383 kΩ

8.2.2.3 Output Inductor Selection

To calculate the value of the output inductor, use Equation 15. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. In general, KIND is normally from 0.1 to 0.3 for the majority of applications.

For this design example, use KIND = 0.2 and the inductor value is calculated to be 3.6 µH. For this design, a nearest standard value was chosen: 4.7 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 16 and Equation 17.

Equation 15. eq10_lvsaa3.gif
Equation 16. eq11_lvsaa3.gif
Equation 17. eq12_lvsaa3.gif
Equation 18. eq13_lvsaa3.gif

8.2.2.4 Output Capacitor

There are two primary considerations for selecting the value of the output capacitor. The output capacitors are selected to meet load transient and output ripple’s requirements.

Equation 19 gives the minimum output capacitance to meet the transient specification. For this example,
LO = 4.7 µH, ΔIOUT = 1.5 A – 0.75 A = 0.75 A and ΔVOUT = 120 mV. Using these numbers gives a minimum capacitance of 18 µF. A standard 22-µF ceramic capacitor is chose in the design.

Equation 19. eq14_lvsaa3.gif

Equation 20 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. From Equation 16, the output current ripple is 0.46 A. From Equation 20, the minimum output capacitance meeting the output voltage ripple requirement is 1.74 µF.

Equation 20. eq15_lvsaa3.gif

Additional capacitance de-rating for aging, temperature and DC bias should influence this minimum value. For this example, one 22-µF, 6.3-V X7R ceramic capacitor with 3 mΩ of ESR will be used.

8.2.2.5 Input Capacitor

A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These capacitors should be connected as close as physically possible to the input pins of the converters as they handle the RMS ripple current shown in Equation 21. For this example, IOUT = 3 A, VOUT = 1.2 V, VINmin = 9.6 V, from Equation 21, the input capacitors must support a ripple current of 0.99 A RMS.

Equation 21. eq16_lvsaa3.gif

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 22. Using the design example values, IOUTmax = 3 A, CIN = 10 µF, fSW = 500 kHz, yields an input voltage ripple of 150 mV.

Equation 22. eq17_lvsaa3.gif

8.2.2.6 Soft-Start Capacitor

The soft-start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power-up. This is useful if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level.

The soft-start capacitor value can be calculated using Equation 23. In this example, the converter’s soft-start time is 0.8 ms. In TPS65251-x, Iss is 5 µA and Vref is 0.8 V. From Equation 23, the soft-start capacitance is 5 nF. A standard 4.7-nF ceramic capacitor is chosen in this design. In this example, C16 is 4.7 nF

Equation 23. eq17_soft_strt_lvsaa4.gif

8.2.2.7 Bootstrap Capacitor Selection

A 0.047-µF ceramic capacitor must be connected between the BST to LX pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or higher voltage rating.

8.2.2.8 Adjustable Current Limiting Resistor Selection

The converter uses the voltage drop on the high-side MOSFET to measure the inductor current. The overcurrent protection threshold can be optimized by changing the trip resistor. Figure 6 governs the threshold of overcurrent protection for Buck 1. When selecting a resistor, do not exceed the graph limits. In this example, the over current threshold is 3.2 A. In order to prevent a premature limit trip, the minimum line is used and the resistor is 86.6 kΩ.

When setting high-side current limit to large current values, ensure that the additional load immediately prior to an overcurrent condition will not cause the switching node voltage to exceed 20 V. Additionally, ensure during worst case operation, with all bucks loaded immediately prior to current limit, the maximum virtual junction temperature of the device does not exceed 125°C.

8.2.2.9 Output Voltage and Feedback Resistors Selection

For the example design, 40.2 kΩ was selected for R10. Vout is 1.2 V, Vref = 0.8 V. Using Equation 24, R11 is calculated as 80.4 kΩ. A standard 80.6-kΩ resistor is chose in this design.

Equation 24. eq19_vo_r11_lvsaa4.gif

8.2.2.10 Compensation

A type-II compensation circuit is adequate for the converter to have a phase margin between 60 and 90 degrees. The following equations show the procedure of designing a peak current mode control dc/dc converter.

The compensation design takes the following steps:

  1. Set up the anticipated cross-over frequency. In this example, the anticipated cross-over frequency (fc) is 65 kHz. The power stage gain (gmPS ) is 10 A/V and the GM amplifier gain (gM ) is 130 µA/V.
  2. Equation 25. eq20_r12_lvsaa4.gif
  3. Place compensation zero at low frequency to boost the phase margin at the crossover frequency. From the procedures above, the compensation network includes a 20-kΩ resistor (R12) and a 4700-pF capacitor (C1).
  4. An additional pole can be added to attenuate high frequency noise.

From the procedures above, the compensation network includes a 20-kΩ resistor (R12) and a 4700-pF capacitor (C14).

8.2.2.11 3.3-V and 6.5-V LDO Regulators

The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:

  • 10 µF for V7V pin 28
  • 3.3 µF to 10 µF for V3V pin 29

8.2.3 Application Curves

typ_cha_buck1_1_SLVSC70.gif
Figure 25. Buck 1 Start-Up (Ch3 = VIN)
typ_cha_buck1_3_SLVSC70.gif
Figure 27. Buck 1 Start-Up 1.5-A Resistive
typ_cha_buck1_5_SLVSC70.gif
Figure 29. Buck 1 Switching Node, No Load
typ_cha_buck1_7_SLVSC70.gif
Figure 31. Buck 1 Switching Node, 2-A Load
typ_cha_buck1_9_SLVSC70.gif
Figure 33. Buck 1 Dynamic Response, 0- to 1-A Step
typ_cha_buck1_11_SLVSC70.gif
Figure 35. Buck 1 Dynamic Response, 1-A to 3-A Step
typ_cha_buck1_13_SLVSC70.gif
Figure 37. Buck 1 Ripple, 2-A Load
typ_cha_buck1_15_SLVSC70.gif
Ch1 = VOUT Ch2 = COMP1 Ch3 = IOUT
Ch4 = Inductor
Figure 39. Buck 1 Current Limit Operation With Slow Rising Output Current, Trip at 4 A
typ_cha_buck1_17_SLVSC70.gif
Figure 41. Buck 1 Low-Power Output, No Load
typ_cha_buck1_19_SLVSC70.gif
Ch1 = VOUT Ch3 = IOUT Ch4 = Inductor
Figure 43. Buck 1 PFM to PWM Transition
typ_cha_buck2_1_SLVSC70.gif
Ch3 = VIN
Figure 45. Buck 2 Start-Up, No Load
typ_cha_buck2_3_SLVSC70.gif
Figure 47. Buck 2 Switching Node, No Load
typ_cha_buck2_5_SLVSC70.gif
Figure 49. Buck 2 Switching Node, 2-A Load
typ_cha_buck2_7_SLVSC70.gif
Figure 51. Buck 2 Dynamic Response, 1-A to 2-A Step
typ_cha_buck2_9_SLVSC70.gif
Figure 53. Buck 2 Ripple, 1-A Load
typ_cha_buck2_11_SLVSC70.gif
Figure 55. Buck 2 Low-Power Output, No Load
typ_cha_buck2_13_SLVSC70.gif
Ch1 = VOUT Ch3 = IOUT Ch4 = Inductor
Figure 57. Buck 2 PWM to PFM Transition
typ_cha_buck3_1_SLVSC70.gif
Ch3 = VIN
Figure 59. Buck 3 Start-Up
typ_cha_buck3_3_SLVSC70.gif
Figure 61. Buck 3 Switching Node, No Load
typ_cha_buck3_5_SLVSC70.gif
Figure 63. Buck 3 Switching Node, 1.5-A Load
typ_cha_buck3_7_SLVSC70.gif
Figure 65. Buck 3 Dynamic Response, 1-A to 1.5-A Step
typ_cha_buck3_9_SLVSC70.gif
Figure 67. Buck 3 Ripple, 1-A Load
typ_cha_buck3_11_SLVSC70.gif
Figure 69. Buck 3 Low-Power Output, No Load
typ_cha_buck3_13_SLVSC70.gif
Ch1 = VOUT Ch3 = IOUT Ch4 = Inductor
Figure 71. Buck 3 PWM to PFM Transition
temp_prof_SLVSC70.gif
Figure 73. Temperature Profile, VO = 1.2 V, IO = 3 A, VO = 1.8 V, IO = 2 A, VO = 3.3 V, IO = 2 A, TA = 28°C
typ_cha_buck1_2_SLVSC70.gif
Figure 26. Buck 1 Soft-Start
typ_cha_buck1_4_SLVSC70.gif
Figure 28. Buck 1 Soft-Start 2-A Load
typ_cha_buck1_6_SLVSC70.gif
Figure 30. Buck 1 Switching Node, 1-A Load
typ_cha_buck1_8_SLVSC70.gif
Figure 32. Buck 1 Switching Node, 3-A Load
typ_cha_buck1_10_SLVSC70.gif
Figure 34. Buck 1 Dynamic Response, 2-A to 3-A Step
typ_cha_buck1_12_SLVSC70.gif
Figure 36. Buck 1 Ripple, 1-A Load
typ_cha_buck1_14_SLVSC70.gif
Figure 38. Buck 1 Ripple, 3-A Load
typ_cha_buck1_16_SLVSC70.gif
Ch1 = VOUT Ch2 = COMP1 Ch3 = IOUT
Ch4 = Inductor
Figure 40. Buck 1 Current Limit Operation, Hiccup
typ_cha_buck1_18_SLVSC70.gif
Figure 42. Buck 1 Low-Power Operation
typ_cha_buck1_20_SLVSC70.gif
Ch1 = VOUT Ch3 = IOUT Ch4 = Inductor
Figure 44. Buck 1 PWM to PFM Transition
typ_cha_buck2_2_SLVSC70.gif
Figure 46. Buck 2 Start-Up, 2-A Load
typ_cha_buck2_4_SLVSC70.gif
Figure 48. Buck 2 Switching Node, 1-A Load
typ_cha_buck2_6_SLVSC70.gif
Figure 50. Buck 2 Dynamic Response, 0-A to 1-A Step
typ_cha_buck2_8_SLVSC70.gif
Figure 52. Buck 2 Ripple, No Load
typ_cha_buck2_10_SLVSC70.gif
Figure 54. Buck 2 Ripple, 3-A Load
typ_cha_buck2_12_SLVSC70.gif
Ch1 = VOUT Ch3 = IOUT Ch4 = Inductor
Figure 56. Buck 2 PFM to PWM Transition
typ_cha_buck2_14_SLVSC70.gif
Ch1 = VOUT Ch2 = COMP1 Ch3 = IOUT
Ch4 = Inductor
Figure 58. Buck 2 Current Limit Operation
typ_cha_buck3_2_SLVSC70.gif
Figure 60. Buck 3 Soft-Start
typ_cha_buck3_4_SLVSC70.gif
Figure 62. Buck 3 Switching Node, 1-A Load
typ_cha_buck3_6_SLVSC70.gif
Figure 64. Buck 3 Dynamic Response, 0-A to 1-A Step
typ_cha_buck3_8_SLVSC70.gif
Figure 66. Buck 3 Ripple, No Load
typ_cha_buck3_10_SLVSC70.gif
Figure 68. Buck 3 Ripple, 3-A Load
typ_cha_buck3_12_SLVSC70.gif
Ch1 = VOUT Ch3 = IOUT Ch4 = Inductor
Figure 70. Buck 3 PFM to PWM Transition
typ_cha_buck3_14_SLVSC70.gif
Ch1 = VOUT Ch2 = COMP1 Ch3 = IOUT
Ch4 = Inductor
Figure 72. Buck 3 Current Limit Operation