SLVSC70A January   2015  – January 2015 TPS65251-1 , TPS65251-2 , TPS65251-3


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics for Buck 1
    7. 6.7 Typical Characteristics for Buck 2
    8. 6.8 Typical Characteristics for Buck 3
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjustable Switching Frequency
      2. 7.3.2  Synchronization
      3. 7.3.3  Out-of-Phase Operation
      4. 7.3.4  Delayed Start-Up
      5. 7.3.5  Soft-Start Time
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Input Capacitor
      8. 7.3.8  Bootstrap Capacitor
      9. 7.3.9  Error Amplifier
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power Good
      12. 7.3.12 3.3-V and 6.5-V LDO Regulators
      13. 7.3.13 Current Limit Protection
      14. 7.3.14 Overvoltage Transient Protection (OVP)
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Power/Pulse Skipping Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Loop Compensation Circuit
        2.  Selecting the Switching Frequency
        3.  Output Inductor Selection
        4.  Output Capacitor
        5.  Input Capacitor
        6.  Soft-Start Capacitor
        7.  Bootstrap Capacitor Selection
        8.  Adjustable Current Limiting Resistor Selection
        9.  Output Voltage and Feedback Resistors Selection
        10. Compensation
        11. 3.3-V and 6.5-V LDO Regulators
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



7 Detailed Description

7.1 Overview

TPS65251-x is a power management IC with three step-down buck converters. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. TPS65251-x can support 4.5- to 18-V input supply, high load current, 300-kHz to 2.2-MHz clocking. The buck converters have an optional PSM mode, which can improve power dissipation during light loads. Alternatively, the device implements a constant frequency mode by connecting the LOW_P pin to ground. The wide switching frequency of 300 kHz to 2.2 MHz allows for efficiency and size optimization. The switching frequency is adjustable by selecting a resistor to ground on the ROSC pin. The SYNC pin also provides a means to synchronize the power converter to an external signal. Input ripple is reduced by 180° out-of-phase operation between Buck 1 and Buck 2. Buck 3 operates in phase with Buck 2.

All three buck converters have peak current mode control which simplifies external frequency compensation. A traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover, an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and makes the crossover frequency over 100 kHz.

Each buck converter has an individual current limit, which can be set up by a resistor to ground from the RLIM pin. The adjustable current limiting enables high-efficiency design with smaller and less expensive inductors.

The device has two built-in LDO regulators. During a standby mode, the 3.3-V LDO and the 6.5-V LDO can be used to drive MCU and other active loads. By this, the system is able to turn off the three buck converters and improve the standby efficiency.

The device has a power-good comparator monitoring the output voltage. Each converter has its own soft-start and enable pins, which provide independent control and programmable soft-start.

7.2 Functional Block Diagram


7.3 Feature Description

7.3.1 Adjustable Switching Frequency

To select the internal switching frequency, connect a resistor from ROSC to ground. Figure 19 shows the required resistance for a given switching frequency.

swi_freq_SLVSC70.gifFigure 19. ROSC vs Switching Frequency
Equation 1. eq1_lvsaa4.gif

For operation at 800 kHz, a 230-kΩ resistor is required.

7.3.2 Synchronization

The status of the SYNC pin is ignored during start-up and the TPS65251’s control only synchronizes to an external signal after the PGOOD signal is asserted. The status of the SYNC pin is ignored during start-up and the TPS65251 only synchronizes to an external clock if the PGOOD signal is asserted. When synchronization is applied, the PWM oscillator frequency must be lower than the sync pulse frequency to allow the external signal trumping the oscillator pulse reliably. When synchronization is not applied, the SYNC pin should be connected to ground.

7.3.3 Out-of-Phase Operation

Buck 1 has a low conduction resistance compared to Buck 2 and 3. Normally Buck 1 is used to drive higher system loads. Buck 2 and 3 are used to drive some peripheral loads like I/O and line drivers. The combination of Buck 2's and Buck 3’s loads may be on par with Buck 1’s load. To reduce input ripple current, Buck 2 operates in phase with Buck 3; Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system, having less input ripple, to lower component cost, save board space, and reduce EMI.

7.3.4 Delayed Start-Up

If a delayed start-up is required on any of the buck converters, fit a ceramic capacitor to the ENx pins. The delay added is approximately 1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1-µA pull-up to the 3V3 rail.

7.3.5 Soft-Start Time

The device has an internal pullup current source of 5 µA that charges an external slow-start capacitor to implement a slow-start time. Equation 2 shows how to select a slow-start capacitor based on an expected slow-start time. The voltage reference (VREF) is 0.8 V and the slow-start charge current (Iss) is 5 µA. The soft-start circuit requires 1 nF per 200 µs to be connected at the SS pin. A 1-ms soft-start time is implemented for all converters fitting 4.7 nF to the relevant pins.

Equation 2. eq2_lvsaa3.gif
td_SLVSC70.gifFigure 20. TPS65251-x Timing Diagram

7.3.6 Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends to use 1% tolerance or better divider resistors. To improve efficiency at light load, start with 40.2 kΩ for the R1 resistor and use Equation 3 to calculate R2.

Equation 3. eq3_lvsaa3.gif
vol_div_cir_SLVSC70.gifFigure 21. Voltage Divider Circuit

7.3.7 Input Capacitor

Use 10-µF X7R/X5R ceramic capacitors at the input of the converter inputs. Connect these capacitors as close as physically possible to the input pins of the converters.

7.3.8 Bootstrap Capacitor

The device has three integrated boot regulators and requires a small ceramic capacitor between the BST and LX pin to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be 0.047 µF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric because of the stable characteristics over temperature and voltage.

7.3.9 Error Amplifier

The device has a transconductance error amplifier. The frequency compensation network is connected between the COMP pin and ground.

7.3.10 Slope Compensation

The device has a built-in slope compensation ramp. The slope compensation can prevent subharmonic oscillations in peak current mode control.

7.3.11 Power Good

The PGOOD pin is an open-drain output. The PGOOD pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. TI recommends to use a pullup resistor from the PGOOD to the output of Buck 1. The PGOOD is pulled up when all three buck converters’ outputs are more than 90% of its nominal output voltage.

The reset time of the PGOOD pin varies according to the part:

  • TPS65251-1 is 1 s.
  • TPS65251-2 is 32 ms.
  • TPS65251-3 is 256 ms.

The polarity of the PGOOD pin is active high.

7.3.12 3.3-V and 6.5-V LDO Regulators

The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:

  • 10 µF for V7V pin 28
  • 3.3 µF for V3V pin 29

7.3.13 Current Limit Protection

All converters operate in hiccup mode: After an overcurrent event lasting more than 10 ms is sensed in any of the converters, all the converters shut down for 10 ms, then the start-up sequencing is retried. If the overload has been removed, the converter ramps up and operates normally. If this is not the case, the converter senses another overcurrent event and shuts down again, repeating the cycle (hiccup) until the failure is cleared.

If an overload condition lasts for <10 ms, only the relevant affected converter goes into and out of under voltage and no global hiccup mode occurs. The converter is protected by the cycle-by-cycle current limit during that time.

7.3.14 Overvoltage Transient Protection (OVP)

The device incorporates an OVP circuit to minimize voltage overshoot. The OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold, which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops below the lower OVP threshold, which is 107%, the high-side MOSFET is allowed to turn on the next clock cycle.

7.3.15 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip threshold. After the die temperature decreases below 140°C, the device reinitiates the power-up sequence. The thermal shutdown hysteresis is 20°C.

7.4 Device Functional Modes

7.4.1 Low-Power/Pulse Skipping Operation

When a synchronous buck converter operates at light load or standby conditions, the switching losses are the dominant source of power losses. Under these load conditions, TPS65251-x uses a pulse skipping modulation technique to reduce the switching losses by keeping the power transistors in the off-state for several switching cycles, while maintaining a regulated output voltage. Figure 22 shows the output voltage and load plus the inductor current.

slope_comp_SLVSC70.gifFigure 22. Low Power/Pulse Skipping

During the burst mode, the converter continuously charges up the output capacitor until the output voltage reaches a certain limit threshold. The operation of the converter in this interval is equivalent to the peak inductor current mode control. In each switch period, the main switch is turned on until the inductor current reaches the peak current limit threshold. As the load increases, the number of pulses increases to make sure that the output voltage stays within regulation limits. When the load is very light, the low-power controller has a zero crossing detector to allow the low-side MOSFET to operate even in light load conditions. The transistor is not disabled at light loads. A zero crossing detection circuit disables it when inductor current reverses. During the whole process, the body diode does not conduct, but is used as blocking diode only.

During the skipping interval, the upper and lower transistors are turned off and the converter stays in idle mode. The output capacitors are discharged by the load current until the moment when the output voltage drops to a low threshold.

The choice of output filter influences the performance of the low-power circuit. The maximum ripple during low-power mode can be calculated as:

Equation 4. eq13_Voutripple_slvsc70.gif


  • KRIP is 1.4 for Buck 1.
  • KRIP is 0.7 for Buck 2 and Buck 3.

TS can be calculated as:

Equation 5. eq14_Ts_slvsc70.gif