SLVSC70A January   2015  – January 2015 TPS65251-1 , TPS65251-2 , TPS65251-3


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics for Buck 1
    7. 6.7 Typical Characteristics for Buck 2
    8. 6.8 Typical Characteristics for Buck 3
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjustable Switching Frequency
      2. 7.3.2  Synchronization
      3. 7.3.3  Out-of-Phase Operation
      4. 7.3.4  Delayed Start-Up
      5. 7.3.5  Soft-Start Time
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Input Capacitor
      8. 7.3.8  Bootstrap Capacitor
      9. 7.3.9  Error Amplifier
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power Good
      12. 7.3.12 3.3-V and 6.5-V LDO Regulators
      13. 7.3.13 Current Limit Protection
      14. 7.3.14 Overvoltage Transient Protection (OVP)
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Power/Pulse Skipping Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Loop Compensation Circuit
        2.  Selecting the Switching Frequency
        3.  Output Inductor Selection
        4.  Output Capacitor
        5.  Input Capacitor
        6.  Soft-Start Capacitor
        7.  Bootstrap Capacitor Selection
        8.  Adjustable Current Limiting Resistor Selection
        9.  Output Voltage and Feedback Resistors Selection
        10. Compensation
        11. 3.3-V and 6.5-V LDO Regulators
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



10 Layout

10.1 Layout Guidelines

Layout is a critical portion of PMIC designs.

  • Place VOUT, and LX on the top layer and an inner power plane for VIN.
  • Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with ground.
  • The top layer ground area sould be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter cpacitor and directly under the TPS65251-x device to provide a thermal path from the Powerpad land to ground.
  • The AGND pin should be tied directly to the power pad under the IC and the power pad.
  • For operation at full rated load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating area.
  • There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching node, the output inductor should be located close to the LX pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
  • The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width.
  • The compensation should be as close as possible to the COMP pins. The COMP and OSC pins are sensitive to noise so the components associated to these pins should be located as close as possible to the IC and routed with minimal lengths of trace.

10.2 Layout Example

TPS65251 LAYOUT.gifFigure 74. Layout Schematic