SLVSC70A January   2015  – January 2015 TPS65251-1 , TPS65251-2 , TPS65251-3

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics for Buck 1
    7. 6.7 Typical Characteristics for Buck 2
    8. 6.8 Typical Characteristics for Buck 3
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjustable Switching Frequency
      2. 7.3.2  Synchronization
      3. 7.3.3  Out-of-Phase Operation
      4. 7.3.4  Delayed Start-Up
      5. 7.3.5  Soft-Start Time
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Input Capacitor
      8. 7.3.8  Bootstrap Capacitor
      9. 7.3.9  Error Amplifier
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power Good
      12. 7.3.12 3.3-V and 6.5-V LDO Regulators
      13. 7.3.13 Current Limit Protection
      14. 7.3.14 Overvoltage Transient Protection (OVP)
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Power/Pulse Skipping Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Loop Compensation Circuit
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Soft-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Adjustable Current Limiting Resistor Selection
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 3.3-V and 6.5-V LDO Regulators
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage VIN1,VIN2, VIN3, LX1, LX2, LX3 –0.3 18 V
LX1, LX2, LX3 (maximum withstand voltage transient <10 ns) –1 18 V
BST1, BST2, BST3, referenced to Lx pin –0.3 7 V
V7V –0.3 7 V
V3V, RLIM1, RLIM2, RLIM3, EN1, EN2, EN3, SS1, SS2,SS3, FB1, FB2, FB3, PGOOD, SYNC, ROSC, RST_IN, LOW_P, COMP1, COMP2, COMP3 –0.3 3.6 V
AGND, GND –0.3 0.3 V
TJ Operating virtual junction temperature –40 125 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input operating voltage 4.5 18 V
TJ Junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS65251-x UNIT
RHA
40 PINS
RθJA Junction-to-ambient thermal resistance 32.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 21.4
RθJB Junction-to-board thermal resistance 8.3
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter N/A
RθJC(bot) Junction-to-case (bottom) thermal resistance 2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V, ƒSW = 500 Hz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
VIN Input voltage range 4.5 18 V
IDDSDN Shutdown EN pin = Low for all converters 175 µA
IDDQ Quiescent, low power disabled (Lo) Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V,
L = 4.7 µH , ƒSW = 800 kHz
20 mA
IDDQ_LOW_P Quiescent, low power enabled (Hi) Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V,
L = 4.7 µH , ƒSW = 800 kHz
1 mA
UVLOVIN VIN undervoltage lockout Rising VIN 4.22 V
Falling VIN 4.1
UVLODEGLITCH Both edges 110 µs
V3p3 Internal biasing supply 3.3 V
V7V Internal biasing supply 6.25 V
V7VUVLO UVLO for internal V7V rail Rising V7V 3.8 V
Falling V7V 3.6
V7VUVLO_DEGLITCH Falling edge 110 µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT START, SWITCHING FREQUENCY AND SYNC CIRCUIT, LOW POWER MODE)
VIH Enable threshold high External GPIO mode, V3p3 = 3.2 to 3.4 V 0.66 x V3p3 V
Enable high level V3p3 = 3.2 to 3.4 V, VENX rising 1.55 1.67 1.82
VIL Enable threshold low External GPIO mode, V3p3 = 3.2 to 3.4 V 0.33 x V3p3 V
Enable low level V3p3 = 3.2 to 3.4 V, VENX falling 0.98 1.10 1.24
REN_DIS Enable discharge resistor –25% 2.1 25%
ICHEN Pullup current enable pin 1.1 µA
tD Discharge time enable pins Power-up 10 ms
ISS Soft-start pin current source 5 µA
FSW_BK Converter switching frequency range Set externally with resistor 0.3 2.2 MHz
RFSW Frequency setting resistor Depending on set frequency 50 600
ƒSW_TOL Internal oscillator accuracy ƒSW = 800 kHz –10% 10%
VSYNCH External clock threshold high V3p3 = 3.3 V 1.24 V
VSYNCL External clock threshold low V3p3 = 3.3 V 1.55 V
SYNCRANGE Synchronization range 0.2 2.2 MHz
SYNCCLK_MIN Sync signal minimum duty cycle 40%
SYNCCLK_MAX Sync signal maximum duty cycle 60%
VIHLOW_P Low power mode threshold high V3p3 = 3.3 V, VENX rising 1.55 V
VILLOW_P Low power mode threshold Low V3p3 = 3.3 V, VENX falling 1.24 V
FEEDBACK, REGULATION, OUTPUT STAGE
VFB Feedback voltage VIN = 12 V, TJ = 25°C –1% 0.8 1% V
VIN = 4.5 to 18 V –2% 0.8 2%
IFB Feedback leakage current 50 nA
tON_MIN Minimum on-time
(current sense blanking) to specify output regulation
70 100 ns
RLIM1 Limit resistance range VIN = 12 V, ƒSW = 500 kHz 75 300
RLIM2,3 Limit resistance range VIN = 12 V, ƒSW = 500 kHz 1.1 5.1 A
ILIM1 Buck1 current limit range VIN = 12 V, ƒSW = 500 kHz 100 300
ILIM2 Buck2 current limit range VIN = 12 V, ƒSW = 500 kHz 1.2 4.1 A
ILIM3 Buck3 current limit range VIN = 12 V, ƒSW = 500 kHz 1.2 4.1 A
MOSFET (BUCK 1)
H.S. Switch Turn-on resistance high-side FET on CH1 BOOT = 6.5 V, TJ = 25°C 95
L.S. Switch Turn-on resistance low-side FET on CH1 VIN = 12 V, TJ = 25°C 50
MOSFET (BUCK 2)
H.S. Switch Turn-on resistance high-side FET on CH2 BOOT = 6.5 V, TJ = 25°C 120
L.S. Switch Turn-on resistance low-side FET on CH2 VIN = 12 V, TJ = 25°C 80
MOSFET (BUCK 3)
H.S. Switch Turn-on resistance high-side FET on CH3 BOOT = 6.5 V, TJ = 25°C 120
L.S. Switch Turn-on resistance low-side FET on CH3 VIN = 12 V, TJ = 25°C 80
ERROR AMPLIFIER
gM Error amplifier transconductance –2 µA < ICOMP < 2 µA 130 µmhos
gmPS COMP to ILX gM ILX = 0.5 A 10 A/V
POWER GOOD RESET GENERATOR
VUVBUCKX Threshold voltage for buck under voltage Output falling 85%
Output rising (PG is asserted) 90%
tUV_deglitch Deglitch time (both edges) Each buck 11 ms
tON_HICCUP Hiccup mode ON time VUVBUCKX asserted 13 ms
tOFF_HICCUP Hiccup mode OFF time All converters disabled. After tOFF_HICCUP elapses, all converters go through sequencing again. 11 ms
VOVBUCKX Threshold voltage for buck over voltage Output rising (high-side FET is forced off) 106%
Output falling (high-side FET is allowed to switch) 104%
tRP Minimum reset period TPS65251-1 1000 ms
TPS65251-2 32
TPS65251-3 256
THERMAL SHUTDOWN
TTRIP Thermal shutdown trip point Rising temperature 160  °C
THYST Thermal shutdown hysteresis Device restarts 20 °C
tTRIP_DEGLITCH Thermal shutdown deglitch 100 120 µs

6.6 Typical Characteristics for Buck 1

TA = 25°C, VIN = 12 V, VO = 1.2 V, L = 4.7 µH, CO = 68 µF, ƒSW = 500 Hz (unless otherwise noted)
typ_cha_buck1_21_SLVSC70.gif
L = 4.7 µH, 20 mΩ
Figure 1. Efficiency, Forced PWM
typ_cha_buck1_23_SLVSC70.gif
L = 4.7 µH, 20 mΩ
Figure 3. Efficiency, LOW_P Mode, 0 to 500 mA
typ_cha_buck1_25_SLVSC70.gif
Figure 5. Line Regulation, Load = 1 A
typ_cha_buck1_22_SLVSC70.gif
L = 4.7 µH, 20 mΩ
Figure 2. Efficiency, LOW_P Mode
typ_cha_buck1_24_SLVSC70.gif
Figure 4. Load Regulation, 25°C, 1% 100-PPM Resistor
typ_cha_buck1_26_SLVSC70.gifFigure 6. Current Limit VIN = 12 V, ƒSW = 500 KHz

6.7 Typical Characteristics for Buck 2

TA = 25°C, VIN = 12 V, VO = 1.8 V, L = 4.7 µH, CO = 68 µF, ƒSW = 500 Hz (unless otherwise noted)
typ_cha_buck2_15_SLVSC70.gif
L = 4.7 µH, 27 mΩ
Figure 7. Efficiency, Forced PWM
typ_cha_buck2_17_SLVSC70.gif
L = 4.7 µH, 27 mΩ
Figure 9. Efficiency, LOW_P Mode, 0 to 500 mA
typ_cha_buck2_19_SLVSC70.gif
Figure 11. Line Regulation, Load = 1 A
typ_cha_buck2_16_SLVSC70.gif
L = 4.7 µH, 27 mΩ
Figure 8. Efficiency, LOW_P Mode
typ_cha_buck2_18_SLVSC70.gif
Figure 10. Load Regulation, 25°C, 1% 100-PPM Resistor
typ_cha_buck2_20_SLVSC70.gifFigure 12. Current Limit VIN = 12 V, ƒSW = 500 kHz

6.8 Typical Characteristics for Buck 3

TA = 25°C, VIN = 12 V, VO = 3.3 V, L = 4.7 µH, CO = 68 µF, ƒSW = 500 Hz (unless otherwise noted)
typ_cha_buck3_15_SLVSC70.gif
L = 4.7 µH, 27 mΩ
Figure 13. Efficiency, Forced PWM
typ_cha_buck3_17_SLVSC70.gif
L = 4.7 µH, 27 mΩ
Figure 15. Efficiency, LOW_P Mode, 0 to 500 mA
typ_cha_buck3_19_SLVSC70.gif
Figure 17. Line Regulation, Load = 1 A
typ_cha_buck3_16_SLVSC70.gif
L = 4.7 µH, 27 mΩ
Figure 14. Efficiency, LOW_P Mode
typ_cha_buck3_18_SLVSC70.gif
Figure 16. Load Regulation, 25°C, 1% 100-PPM Resistor
typ_cha_buck3_20_SLVSC70.gif
Figure 18. Current Limit VIN = 12 V, ƒSW = 500 KHz