SWCS048G March   2010  – September 2014 TPS65921

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Resistance Characteristics for ZQZ Package
    5. 4.5  Crystal Oscillator
    6. 4.6  Clock Slicer
    7. 4.7  32KCLKOUT Output Clock
    8. 4.8  HFCLKOUT Output Clock
    9. 4.9  VDD1 DC-DC Converter
    10. 4.10 VDD2 DC-DC Converter
    11. 4.11 VIO DC-DC Converter
    12. 4.12 VMMC1 Low Dropout Regulator
    13. 4.13 VDAC Low Dropout Regulator
    14. 4.14 VAUX2 Low Dropout Regulator
    15. 4.15 VPLL1 Low Dropout Regulator
    16. 4.16 Internal LDOs
    17. 4.17 Voltage References
    18. 4.18 Battery Threshold Levels
    19. 4.19 Power Consumption
    20. 4.20 USB Charge Pump
    21. 4.21 Hot-Die Detection and Thermal Shutdown
    22. 4.22 USB
      1. 4.22.1  LS/FS Single-Ended Receivers
      2. 4.22.2  LS/FS Differential Receiver
      3. 4.22.3  LS/FS Transmitter
      4. 4.22.4  FS Transmitter
      5. 4.22.5  HS Differential Receiver
      6. 4.22.6  HS Transmitter
      7. 4.22.7  UART Transceiver
      8. 4.22.8  Pullup/Pulldown Resistors
      9. 4.22.9  OTG VBUS
      10. 4.22.10 OTG ID
      11. 4.22.11 USB Charger Detection
    23. 4.23 MADC
      1. 4.23.1 MADC Analog Input Range and Prescaler Ratio
      2. 4.23.2 MADC Power Consumption
    24. 4.24 TPS65921 Interface Target Frequencies
      1. 4.24.1 I2C Timing
    25. 4.25 JTAG Interfaces
      1. 4.25.1 JTAG Interface Timing Requirements
      2. 4.25.2 JTAG Interface Switching Characteristics
      3. 4.25.3 Debouncing Time
  5. 5Detailed Description
    1. 5.1 Functional Block Diagram
    2. 5.2 Clock System
    3. 5.3 32-kHz Oscillator
    4. 5.4 Clock Slicer
    5. 5.5 Power Path
      1. 5.5.1 Step-Down Converters
      2. 5.5.2 LDO
      3. 5.5.3 Power Reference
      4. 5.5.4 Power Use Cases
      5. 5.5.5 Power Timing
        1. 5.5.5.1 Switch On In MASTER_C021_GENERIC Mode
        2. 5.5.5.2 Switch On In SLAVE_C021_GENERIC Mode
        3. 5.5.5.3 Switch-Off Sequence
          1. 5.5.5.3.1 Switch-Off Sequence In Master Modes
          2. 5.5.5.3.2 Switch-Off Sequence in Slave Mode
        4. 5.5.5.4 Charge Pump
      6. 5.5.6 USB Transceiver
      7. 5.5.7 PHY
        1. 5.5.7.1 LS/FS Single-Ended Receivers
        2. 5.5.7.2 LS/FS Differential Receiver
        3. 5.5.7.3 LS/FS Transmitter
        4. 5.5.7.4 HS Differential Receiver
        5. 5.5.7.5 HS Differential Transmitter
        6. 5.5.7.6 UART Transceiver
    6. 5.6 Charger Detection
      1. 5.6.1 USB Battery Charger FSM
      2. 5.6.2 FSM Control Signals
    7. 5.7 MADC
    8. 5.8 JTAG Interfaces
      1. 5.8.1 Keyboard
  6. 6Device and Documentation Support
    1. 6.1 Device Support
      1. 6.1.1 Development Support
      2. 6.1.2 Device Nomenclature
    2. 6.2 Documentation Support
      1. 6.2.1 Community Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Export Control Notice
    6. 6.6 Glossary
  7. 7Mechanical Packaging and Orderable Information
    1. 7.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Device Overview

1.1 Features

  • Three Step-Down Converters:
    • Up to 1.2 A of Output Current for VDD1
      • TPS65921B Supports VDD1 up to 1.2 A
      • TPS65921B1 Supports VDD1 up to 1.4 A (Necessary for 1-GHz Operation)
    • SmartReflex™ Dynamic Voltage Management
    • 3.2-MHz Fixed Frequency Operation
    • VIN Range from 2.7 to 4.5 V
    • Typical 30 µA Quiescent per Converter
  • Four General-Purpose Configurable LDOs:
    • Dynamic Voltage Scaling
    • 220-mA Maximum Current for One LDO
    • VIN Range from 2.7 to 4.5 V
    • 2 LDOs With Low Noise and High PSRR
  • RTC With Alarm Wake-Up Mechanism
  • Clock Management
    • 32-kHz Crystal Oscillator
    • Clock Slicer for 26, 19.2, and 38.4 MHz
    • HF Clock Output Buffer
  • USB:
    • USB HS 2.0 Transceiver
    • USB 1.3 OTG-Compliant
    • 12-Bit ULPI 1.1 Interface
    • USB Power Supply (5-V CP for VBUS)
  • Control
    • High-Speed I2C Interface
    • All Resource Configurable by I2C
  • Keypad Interface up to 8 × 8
  • 10-Bit A/D Converter
  • Hot-Die, Thermal Shutdown Protection
  • µ*BGA 120 Balls ZQZ

1.2 Applications

  • Mobile Phones and Smart Phones
  • MP3 Players
  • Handheld Devices
  • E-Books
  • OMAP™ and Low-Power DSP Supply

1.3 Description

The TPS65921 device is a highly integrated power-management circuit (IC) that supports the power and peripheral requirements of the OMAP application processors. The device contains power management, a universal serial bus (USB) high-speed (HS) transceiver, an analog-to-digital converter (ADC), a real-time clock (RTC), a keypad interface, and an embedded power control (EPC). The power portion of the device contains three buck converters, two controllable by a dedicated SmartReflex class-3 interface, multiple low-dropout (LDO) regulators, an EPC to manage the power-sequencing requirements of OMAP, and an RTC module. The USB module provides an HS 2.0 transceiver suitable for direct connection to the OMAP universal transceiver macrocell interface (UTMI) + low pin interface (ULPI) with an integrated charge pump (CP).

The device also provides auxiliary modules: ADC, keypad interface, and general-purpose inputs/outputs (GPIOs) muxed with the JTAG functions. The keypad interface implements a built-in scanning algorithm to decode hardware-based key presses and to reduce software use, with multiple additional GPIOs that can be used as interrupts when they are configured as inputs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
TPS65921ZQZ ZQZ (120) 6.00 mm × 6.00 mm
(1) For more information, see Section 7, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

SWCS048-010.gifFigure 1-1 Functional Block Diagram