SLVS332J March   2001  – December 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Regulator Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Powering Microcontrollers
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Capacitor Requirements
        3. 8.2.1.3 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance.

10.2 Layout Example

TPS79718 TPS797285 TPS79730 TPS79733 TPS797xx_LayoutRecChanges.gif Figure 16. Layout Example

10.3 Power Dissipation and Junction Temperature

Specified regulator operation is ensured for a junction temperature of up to 85°C; restrict the maximum junction temperature to 85°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation (PD(MAX)) and the actual dissipation (PD), which must be less than or equal to PD(MAX).

The maximum-power-dissipation limit is determined using Equation 1.

Equation 1. TPS79718 TPS797285 TPS79730 TPS79733 q_pdmax.gif

where

  • TJ(max) is the maximum allowable junction temperature
  • RθJA is the thermal resistance junction-to-ambient for the package (see Thermal Information)
  • TA is the ambient temperature

The regulator dissipation is calculated using Equation 2.

Equation 2. TPS79718 TPS797285 TPS79730 TPS79733 q_pd.gif

Power dissipation resulting from quiescent current is negligible.