JAJSET0B December   2018  – October 2019 TPS7A26

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable
      2. 8.3.2 Dropout Voltage
      3. 8.3.3 Current Limit
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
      6. 8.3.6 Power Good
      7. 8.3.7 Active Overshoot Pulldown Circuitry
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Functional Mode Comparison
      2. 8.4.2 Normal Operation
      3. 8.4.3 Dropout Operation
      4. 8.4.4 Disabled
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Adjustable Device Feedback Resistors
      2. 9.1.2 Recommended Capacitor Types
      3. 9.1.3 Input and Output Capacitor Requirements
      4. 9.1.4 Reverse Current
      5. 9.1.5 Feed-Forward Capacitor (CFF)
      6. 9.1.6 Power Dissipation (PD)
      7. 9.1.7 Estimating Junction Temperature
      8. 9.1.8 Special Consideration for Line Transient
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transient Response
        2. 9.2.2.2 Selecting Feedback Divider Resistors
        3. 9.2.2.3 Thermal Dissipation
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRV|6
サーマルパッド・メカニカル・データ
発注情報

9.2.2.2 Selecting Feedback Divider Resistors

For this design example, VOUT is set to 5 V. The following equations set the output voltage:

Equation 10. VOUT = VFB × (1 + R1 / R2)
Equation 11. R1 + R2 ≤ VOUT / (IFB × 100)

For improved output accuracy, use Equation 11 and IFB(TYP) = 10 nA as listed in the Electrical Characteristics table to calculate the upper limit for series feedback resistance, R1 + R2 ≤ 5 MΩ.

The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 1.24 V as listed in the Electrical Characteristics table). Use Equation 10 to determine the ratio of R1 / R2 = 3.03. Use this ratio and solve Equation 11 for R2. Now calculate the upper limit for R2 ≤ 1.24 MΩ. Select a standard value resistor of R2 = 1.18 MΩ.

Reference Equation 10 and solve for R1:

Equation 12. R1 = (VOUT / VFB – 1) × R2

From Equation 12, R1 = 3.64 MΩ can be determined. Select a standard resistor value for R1 = 3.6 MΩ. From Equation 10, select VOUT = 5.023 V.