SBVS169D December   2011  – April 2015 TPS7A33

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Enable Pin Operation
      3. 7.3.3 Programmable Soft-Start
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Adjustable Operation
      2. 8.1.2  Capacitor Recommendations
      3. 8.1.3  Input and Output Capacitor Requirements
      4. 8.1.4  Noise Reduction and Feed-Forward Capacitor Requirements
      5. 8.1.5  Post DC-DC Converter Filtering
      6. 8.1.6  Audio Applications
      7. 8.1.7  Maximum AC Performance
      8. 8.1.8  Power-Supply Rejection
      9. 8.1.9  Output Noise
      10. 8.1.10 Transient Response
      11. 8.1.11 Power for Precision Analog
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don’ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Performance and Heat Sink Selection
    4. 10.4 Package Mounting
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

10 Layout

Layout is a critical part of good power-supply design. Several signal paths that conduct fast-changing currents or voltages can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with a X5R or X7R dielectric.

10.1 Layout Guidelines

10.1.1 Improve PSRR and Noise Performance

To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the board with separate planes for IN, OUT, and GND. The IN and OUT planes should be isolated from each other by a GND plane section. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device.

Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized in order to maximize performance and ensure stability. Every capacitor (CIN, COUT, CNR/SS, CFF) must be placed as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability.

10.2 Layout Example

It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout shown in Figure 41 and the schematic shown in Figure 42 have been shown to produce good results and are meant as a guideline.

TPS7A33 ai_RGW_layout_bvs169.gifFigure 40. TPS7A33 5-mm × 5-mm QFN-20 Layout Guideline
TPS7A33 pcb_top_bvs169.pngFigure 41. TPS7A33 TO-220 EVM PCB Layout Example: Top Layer
TPS7A33 pcb_bottom_bvs169.pngFigure 42. TPS7A33 TO-220 EVM PCB Layout Example: Bottom Layer
TPS7A33 sch_bvs169.gifFigure 43. Schematic for TPS7A33 TO-220 EVM PCB Layout Example

10.3 Thermal Performance and Heat Sink Selection

The primary TPS7A33 application is to provide ultralow-noise voltage rails to high-performance analog circuitry in order to maximize system accuracy and precision. The high-current and high-voltage characteristics of this regulator means that, often enough, high power (heat) is dissipated from the device itself. This heat, if dissipated into the PCB (as is the case with SMT packages), creates a temperature gradient in the surrounding area that causes nearby components to react to this temperature change (drift). In high-performance systems, such drift may degrade overall system accuracy and precision.

Compared to surface-mount packages, the TO-220 (KC) package allows for an external heat sink to be used to maximize thermal performance and keep heat from dissipating into the PCB.

The heat generated by the device is a result of the power dissipation, which depends on input voltage and load conditions. Power dissipation (PD) can be approximated by calculating the product of the output current times the voltage drop across the output pass element, as shown in Equation 4:

Equation 4. TPS7A33 q_pd_bvs125.gif

Heat flows from the device to the ambient air through many paths, each of which represents resistance to the heat flow; this effect is called thermal resistance.

The total thermal resistance of a system is defined by: θJA = (TJ – TA)/PD; where: θJA is the thermal resistance (in °C/W), TJ is the allowable juntion temperature of the device (in °C), TA is the maximum temperature of the ambient cooling air (in °C), and PD is the amount of power (heat) dissipated by the device (in W).

Whenever a heat sink is installed, the total thermal resistance (θJA) is the sum of all the individual resistances from the device, going through its case and heatsink to the ambient cooling air (θJA = θJC + θCS + θSA). Realistically, only two resistances can be controlled: θCS and θSA. Therefore, for a device with a known θJC, θCS and θSA become the main design variables in selecting a heat sink.

The thermal interface between the case and the heat sink (θCS) is controlled by selecting the correct heat-conducting material. Once the θCS is selected, the required thermal resistance from the heat sink to ambient is calculated by the following equation: θSA = [(TJ – TA)/PD] – [θJC+ θCS]. This information allows the most appropriate heat sink to be selected for any particular application.

10.4 Package Mounting

The TO-220 (KC) 7-lead, straight-formed package lead spacing poses a challenge when creating a suitable PCB footprint without bending the leads. Component forming pliers can be used to manually bend the package leads into a 7-lead stagger pattern with increased lead spacing that can be more easily used.

The TPS7A33 evaluation board layout can be used as a guideline on suitable PCB footprints, available at www.ti.com. Refer to the TPS7A3301EVM-061 user's guide for more information.