SBVS169D December   2011  – April 2015 TPS7A33

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Enable Pin Operation
      3. 7.3.3 Programmable Soft-Start
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Adjustable Operation
      2. 8.1.2  Capacitor Recommendations
      3. 8.1.3  Input and Output Capacitor Requirements
      4. 8.1.4  Noise Reduction and Feed-Forward Capacitor Requirements
      5. 8.1.5  Post DC-DC Converter Filtering
      6. 8.1.6  Audio Applications
      7. 8.1.7  Maximum AC Performance
      8. 8.1.8  Power-Supply Rejection
      9. 8.1.9  Output Noise
      10. 8.1.10 Transient Response
      11. 8.1.11 Power for Precision Analog
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don’ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Performance and Heat Sink Selection
    4. 10.4 Package Mounting
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage IN pin to GND pin –36 0.3 V
OUT pin to GND pin –33 0.3
OUT pin to IN pin –0.3 36
FB pin to GND pin –2 0.3
FB pin to IN pin –0.3 36
EN pin to GND pin –36 10
NR/SS pin to IN pin –0.3 36
NR/SS pin to GND pin –2 0.3
Current Peak output Internally limited
Temperature Operating virtual junction, TJ –40 150 °C
Storage temperature, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input supply voltage –35 –3 V
VEN Enable supply voltage VIN 10 V
VOUT Output voltage –33.2 VREF V
IOUT Output current 0 1 A
R2(1) R2 is the lower feedback resistor 240 kΩ
CIN Input capacitor 10 47 µF
COUT Output capacitor 10 47 µF
CNR Noise reduction capacitor 1 µF
CFF Feed-forward capacitor 10 nF
TJ Operating junction temperature –40 125 °C
(1) This condition helps ensure stability at no load.

6.4 Thermal Information

THERMAL METRIC(1) TPS7A33 UNIT
KC (TO-220) RGW (VQFN)
7 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 31.2 33.7 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 40 30.4
RθJB Junction-to-board thermal resistance 17.4 12.5
ψJT Junction-to-top characterization parameter 6.4 0.4
ψJB Junction-to-board characterization parameter 17.2 12.5
RθJC(bot) Junction-to-case(bottom) thermal resistance 0.8 2.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At –40°C ≤ TJ ≤ 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 10 μF, COUT = 10 μF, CNR/SS = 0 nF, and FB tied to OUT, unless otherwise noted.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage –35 –3 V
VREF Internal reference TJ = 25°C, VFB = VREF –1.192 –1.175 –1.157 V
VUVLO Undervoltage lockout threshold –2 V
VOUT Output voltage range(2) |VIN| ≥ |VOUT(nom)| + 1 V –33.2 VREF V
Nominal accuracy TJ = 25°C, |VIN| = |VOUT(nom)| + 0.5 V –1.5 1.5 %VOUT
Overall accuracy 5 V ≤ |VIN| ≤ 35 V
1 mA ≤ IOUT ≤ 1 A		 ±1 %VOUT
|VOUT(nom)| + 1 V ≤ |VIN| ≤ 35 V
1 mA ≤ IOUT ≤ 1 A		 –2.5 2.5
ΔVOUT(ΔVI) Line regulation |VOUT(nom)| + 1 V ≤ |VIN| ≤ 35 V 0.14 %VOUT
ΔVOUT(ΔIL) Load regulation 1 mA ≤ IOUT ≤ 1 A 0.4 %VOUT
|VDO| Dropout voltage VIN = 95% VOUT(nom), IOUT = 500 mA 290 mV
VIN = 95% VOUT(nom), IOUT = 1 A 325 800
ICL Current limit VOUT = 90% VOUT(nom) 1900 mA
IGND Ground current IOUT = 0 mA 210 350 μA
IOUT = 500 mA 5 mA
|ISHDN| Shutdown supply current VEN = +0.4 V 1 3 μA
VEN = –0.4 V 1 3
IFB Feedback current(3) 14 100 nA
|IEN| Enable current VEN = |VIN| = |VOUT(nom)| + 1 V 0.48 1 μA
VIN = VEN = –35 V 0.51 1
VIN = –35 V, VEN = +10 V 0.5 1
VEN(+HI) Positive enable high-level voltage 2 10 V
VEN(+LO) Positive enable low-level voltage 0 0.4 V
VEN(–HI) Negative enable high-level voltage VIN –2 V
VEN(–LO) Negative enable low-level voltage –0.4 0 V
Vn Output noise voltage VIN = –3 V, VOUT(nom) = VREF, COUT = 22 μF, CNR/SS = 10 nF, BW = 10 Hz to 100 kHz 16 μVRMS
PSRR Power-supply rejection ratio VIN = –6.2 V, VOUT(nom) = –5 V, COUT = 22 μF, CNR/SS = 10 nF, CFF(4) = 10 nF, f = 10 kHz 72 dB
Tsd Thermal shutdown temperature Shutdown, temperature increasing 170 °C
Reset, temperature decreasing 150 °C
TJ Operating junction temperature –40 125 °C
(1) At operating conditions, VIN ≤ 0 V, VOUT(nom) ≤ VREF ≤ 0 V. At regulation, VIN ≤ VOUT(nom) – |VDO|. IOUT > 0 flows from OUT to IN.
(2) To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5 μA is required.
(3) IFB > 0 flows into the device.
(4) CFF refers to a feed-forward capacitor connected between the FB and OUT pins.

6.6 Typical Characteristics

At –40°C ≤ TJ ≤ 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 μF, COUT = 22 μF, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted.
TPS7A33 tc_vfb-vin_bvs169.png
Figure 1. Feedback Voltage vs Input Voltage
TPS7A33 tc_ignd-vin2_bvs169.png
Figure 3. Ground Current vs Input Voltage
TPS7A33 tc_ignd-io_bvs169.png
Figure 5. Ground Current vs Output Current
TPS7A33 tc_iq-vin_bvs169.png
Figure 7. Quiescent Current vs Input Voltage
TPS7A33 tc_vdo-io_bvs169.png
Figure 9. Dropout Voltage vs Output Current
TPS7A33 tc_ven-temp_bvs169.png
Figure 11. Enable Threshold Voltage vs Temperature
TPS7A33 tc_vo-io_bvs169.png
Figure 13. Load Regulation
TPS7A33 tc_psrr-cnr_bvs169.png
Figure 15. Power-Supply Rejection Ratio vs CNR/SS
TPS7A33 tc_psrr-io_bvs169.png
Figure 17. Power-Supply Rejection Ratio vs IOUT
TPS7A33 tc_psrr-vdo_bvs169.png
Figure 19. Power-Supply Rejection Ratio vs VDO
TPS7A33 tc_vonoise-cnr_bvs169.png
Figure 21. Output Spectral Noise Density vs CNR/SS
TPS7A33 tc_load_trans_1-500_bvs169.gif
Figure 23. Load Transient
TPS7A33 tc_line_trans_16-26_bvs169.gif
Figure 25. Line Transient
TPS7A33 tc_cap_soft-start_bvs169.gif
Figure 27. Capacitor-Programmable Soft-Start
TPS7A33 tc_ifb-temp_bvs169.png
Figure 2. Feedback Current vs Temperature
TPS7A33 tc_ignd-vin_bvs169.png
Figure 4. Ground Current vs Input Voltage
TPS7A33 tc_ien-vin_bvs169.png
Figure 6. Enable Current vs Enable Voltage
TPS7A33 tc_ishdn-vin_bvs169.png
Figure 8. Shutdown Current vs Input Voltage
TPS7A33 tc_vdo-temp_bvs169.png
Figure 10. Dropout Voltage vs Temperature
TPS7A33 tc_vo-vin_bvs169.png
Figure 12. Line Regulation
TPS7A33 tc_psrr-cout_bvs169.png
Figure 14. Power-Supply Rejection Ratio vs COUT
TPS7A33 tc_psrr-cff_bvs169.png
Figure 16. Power-Supply Rejection Ratio vs CFF
TPS7A33 tc_psrr-vout_bvs169.png
Figure 18. Power-Supply Rejection Ratio vs VOUT
TPS7A33 tc_vonoise-io_bvs169.png
Figure 20. Output Spectral Noise Density vs Output Current
TPS7A33 tc_vonoise-vo_bvs169.png
Figure 22. Output Spectral Noise Density vs VOUT(nom)
TPS7A33 tc_load_trans_500-1_bvs169.gif
Figure 24. Load Transient
TPS7A33 tc_line_trans_26-16_bvs169.gif
Figure 26. Line Transient