JAJSH18A March   2019  – September 2019

PRODUCTION DATA.

1. 特長
2. アプリケーション
3. 概要
1.     Device Images
4. 改訂履歴
5. 概要（続き）
6. Pin Configuration and Functions
7. Specifications
8. Detailed Description
1. 8.1 Overview
2. 8.2 Functional Block Diagram
3. 8.3 Feature Description
4. 8.4 Device Functional Modes
9. Application and Implementation
1. 9.1 Application Information
2. 9.2 Typical Application
1. 9.2.1 Design Requirements
2. 9.2.2 Detailed Design Procedure
3. 9.2.3 Application Curves
10. 10Power Supply Recommendations
11. 11Layout
12. 12デバイスおよびドキュメントのサポート
1. 12.1 デバイス・サポート
1. 12.1.1 開発サポート
2. 12.1.2 デバイスの項目表記
2. 12.2 ドキュメントのサポート
3. 12.3 ドキュメントの更新通知を受け取る方法
4. 12.4 コミュニティ・リソース
5. 12.5 商標
6. 12.6 静電気放電に関する注意事項
7. 12.7 Glossary
13. 13メカニカル、パッケージ、および注文情報

• PWP|14
• PWP|14

#### 9.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection

Using the device power-fail detection feature is optional as indicated in Figure 14 and Figure 15. The PFD pin is an analog voltage input to an internal comparator that drives the open-drain PF output. The resistor divider consisting of R1 and R2 can be used to set the minimum VSCIN voltage that triggers the PF output. Regardless of whether an AC or DC supply is used, the PF output triggers when the supply fails to maintain the VSCIN voltage above VSCIN (MIN). Equation 22 gives the calculation of the R1 – R2 resistor divider that sets the PF pin trigger point.

Equation 22. VIT(PFD,FALLING) threshold = (VSCIN (MIN) – Vripple on the SCIN pin) × [R2 / (R1+ R2)]

where

• VRipple is the peak-to-peak voltage ripple on the SCIN pin and is in the range of 0.5 V to 0.8 V

Equation 23 calculates the VSCIN (MIN) voltage.

Equation 23. VSCIN (MIN) = 4 (VLDO_OUT (nom) + 0.6 V) – 1.5 V

Set R1 as close as possible to the maximum value specified in the Recommended Operating Conditions table. This high R1 value limits the power used by the resistors, then calculates the value of R2. Choose the closest standard resistor value for R2. Optionally, because the PFD pin is a high-impedance node, add a 10-pF capacitor in parallel with the R2 resistors to reduce noise coupling into VPFD.

Pull up the PF pin to a DC rail, such as VLDO_IN, so that a microcontroller can monitor the PF signal as an early power-fail warning to trigger the switch to a backup power solution or to perform a controlled system shutdown. Pulling up the PF pin to VLDO_IN rather than VLDO_OUT ensures that the PF signal is continuously monitored even if VLDO_OUT is down because of a load-transient event or a short-circuit fault.

NOTE

An external DC rail can also be used to pullup the PF pin signal via a pullup resistor only if the external DC rail shares a common ground with the device GND pins and the absolute maximum of the PF pin voltage is not exceeded.