JAJSDH9D August   2017  – May 2019 TUSB1042I

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      TUSB1042Iのアイ・ダイアグラム
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  DCI Specific Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 USB3.1 Modes
      5. 8.4.5 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 9. General Registers
      2. 8.6.2 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 10. USB3.1 Control/Status Registers (0x20)
      3. 8.6.3 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 11. USB3.1 Control/Status Registers (0x21)
      4. 8.6.4 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
        1. Table 12. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.4 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]

Figure 18. USB3.1 Control/Status Registers (0x22)
7 6 5 4 3 2 1 0
CM_ACTIVE LFPS_EQ U2U3_LFPS_DEBOUNCE DISABLE_U2U3_RXDET DFP_RXDET_INTERVAL USB3_COMPLIANCE_CTRL
R/U R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. USB3.1 Control/Status Registers (0x22)

Bit Field Type Reset Description
7 CM_ACTIVE R/U 0 0 –device not in USB 3.1 compliance mode. (Default)
1 –device in USB 3.1 compliance mode
6 LFPS_EQ R/W 0 Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL and SSEQ_SEL applies to received LFPS signal.
0 – EQ set to zero when receiving LFPS (default)
1 – EQ set to EQ1_SEL, EQ2_SEL, and SSEQ_SEL when receiving LFPS.
5 U2U3_LFPS_DEBOUNCE R/W 0 0 – No debounce of LFPS before U2/U3 exit. (Default)
1 – 200 µs debounce of LFPS before U2/U3 exit.
4 DISABLE_U2U3_RXDET R/W 0 0 – Rx.Detect in U2/U3 enabled. (Default)
1 – Rx.Detect in U2/U3 disabled.
3:2 DFP_RXDET_INTERVAL R/W 01 This field controls the Rx.Detect interval for the Downstream facing port (TX1P/N and TX2P/N).
00 – 8 ms
01 – 12 ms (default)
10 – 48 ms
11 – 96 ms
1:0 USB3_COMPLIANCE_CTRL R/W 00 00 – FSM determined compliance mode. (Default)
01 – Compliance Mode enabled in DFP direction (SSTX -> TX1/TX2)
10 – Compliance Mode enabled in UFP direction (RX1/RX2 -> SSRX)
11 – Compliance Mode Disabled.