SLLS413L February   2000  – June 2017 TUSB2046B , TUSB2046I

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      USB-Tiered Configuration Example
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Differential Driver Switching Characteristics (Full Speed Mode)
    7. 7.7 Differential Driver Switching Characteristics (Low Speed Mode)
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB Power Management
      2. 8.3.2 Clock Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Vendor ID and Product ID With External Serial EEPROM
    5. 8.5 Programming
      1. Table 1. EEPROM Memory Map
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 TUSB2046x Power Supply
    2. 10.2 Downstream Port Power
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Differential Pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Differential Pairs

  1. Must be designed with a differential impedance of 90Ω ±10%.
  2. Route all differential pairs on the same layer adjacent to a solid ground plane.
  3. Do not route differential pairs over any plane split.
  4. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes stub on the differential pair.
  5. Avoid 90-degree turns in trace. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
  6. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for USB 2.0 differential pair signals is 8 inches. Longer trace lengths require very careful routing to assure proper signal integrity.
  7. Match the etch lengths of the differential pair traces. The USB 2.0 differential pairs should not exceed 50 mils relative trace length difference.
  8. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure that the same via type and placement are used for both signals in a pair. Any vias used should be placed as close as possible to the TUSB2046x device.
  9. Do not place power fuses across the differential pair traces.