JAJSG68A September   2018  – December 2018 TUSB217-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High speed boost
      2. 7.3.2 RX Sensitivity
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Speed (LS) mode
      2. 7.4.2 Full Speed (FS) mode
      3. 7.4.3 High Speed (HS) mode
      4. 7.4.4 High Speed downstream port electrical compliance test mode
      5. 7.4.5 Shutdown mode
      6. 7.4.6 I2C mode
    5. 7.5 TUSB217 Registers
      1. 7.5.1 EDGE_BOOST Register (Offset = 0x1) [reset = X]
        1. Table 4. EDGE_BOOST Register Field Descriptions
      2. 7.5.2 CONFIGURATION Register (Offset = 0x3) [reset = X]
        1. Table 5. CONFIGURATION Register Field Descriptions
      3. 7.5.3 DC_BOOST Register (Offset = 0xE) [reset = X]
        1. Table 6. DC_BOOST Register Field Descriptions
      4. 7.5.4 RX_SEN Register (Offset = 0x25) [reset = X]
        1. Table 7. RX_SEN Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGY|14
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
POWER
IACTIVE_HS High Speed Active Current USB channel = HS mode. 480 Mbps traffic. VCC supply stable, with Boost = Max 22 36 mA
IIDLE_HS High Speed Idle Current USB channel = HS mode, no traffic. VCC supply stable, Boost = Max 22 36 mA
IHS_SUPSPEND High Speed Suspend Current USB channel = HS Suspend mode. VCC supply stable 0.75 1.4 mA
IFS Full-Speed Current USB channel = FS mode, 12 Mbps traffic, Vcc supply stable 0.75 1.4 mA
IDISCONN Disconnect Power Host side application. No device attachment. 0.80 1.4 mA
ISHUTDN Shutdown Power RSTN driven low, VCC supply stable 35 95 µA
CONTROL PIN LEAKAGE
ILKG_FS Pin failsafe leakage current for SDA, RSTN VCC = 0 V, pin at VIH, max 10 15 µA
ILKG_FS Pin failsafe leakage current for BOOST,  RX_SEN VCC = 0 V, pin at VIH, max 6 10 µA
ILKG_FS Pin failsafe leakage current for SCL VCC = 0 V, pin at VIH, max 70 nA
INPUT RSTN
VIH High level input voltage 1.5 3.6 V
VIL Low-level input voltage 0 0.5 V
IIH High level input current VIH = 3.6 V, RPU enabled ±15 µA
IIL Low level input current VIL = 0V, RPU enabled ±20 µA
INPUT RX_SEN (3-level input, for mid level leave pin floating)
VIH High level input voltage

RRXSEN1=47kΩ, RRXSEN2=10kΩ
VCC<=4.3V  1.8 3.6 V
VIH High level input voltage

RRXSEN1=37kΩ, RRXSEN2=47kΩ
VCC>4.3V 2.0 3.6 V
VIL Low level input voltage

22kΩ <= RRXSEN1 <= 33kΩ
0.4 V
INPUT BOOST
RBOOST_LVL0 External pulldown resistor for BOOST Level 0 160 Ω
RBOOST_LVL1 External pulldown resistor for BOOST Level 1 1.5 1.8 2 kΩ
RBOOST_LVL2 External pulldown resistor for BOOST Level 2 3.4 3.6 3.96 kΩ
RBOOST_LVL3 External pulldown resistor  for BOOST Level 3 7.5 kΩ
OUTPUTS CD, ENA_HS
VOH High level output voltage IO = –50 µA, VCC >= 3.0V 2.5 V
VOH High level output voltage IO = –50 µA, VCC = 2.3V 1.8 V
VOL Low level output voltage IO = 50 µA 0.3 V
I2C
CI2C_BUS I2C Bus Capacitance 4 150 pF
IOL I2C open drain output current VOL = 0.4V 1.5 mA
VIL VI2C_BUS = 1.8V +/-10% RPull-up =1.6kΩ to 2.5kΩ, % of VI2C_BUS 25 %
VIL VI2C_BUS = 3.3V +/-10% RPull-up =2.8kΩ to 7kΩ, % of VI2C_BUS 25 %
VIH VI2C_BUS = 1.8V +/-10% RPull-up =1.6kΩ to 2.5kΩ, % of VI2C_BUS 75 %
VIH VI2C_BUS = 3.3V +/-10% RPull-up =2.8kΩ to 7kΩ, % of VI2C_BUS 75 %
RPull-up VI2C_BUS = 1.8V +/-10% 1.6 2 2.5 kΩ
RPull-up VI2C_BUS = 3.3V +/-10% 2.8 4.7 7 kΩ
SCL Frequency 100 kHz
DxP, DxM
CIO_DXX Capacitance to GND Measured with VNA at 240 MHz, VCC supply stable, Redriver off 2.5 pF
(1) All typical values are at VCC = 5 V, and TA = 25°C.