JAJSG68A September 2018 – December 2018 TUSB217-Q1
Table 2 lists the memory-mapped registers for the TUSB217 registers. All register offset addresses not listed in Table 2 should be considered as reserved locations and the register contents should not be modified.
|0x1||EDGE_BOOST||This register is setting EDGE BOOST level.||Go|
|0x3||CONFIGURATION||This register is selecting device mode.||Go|
|0xE||DC_BOOST||This register is setting DC BOOST level.||Go|
|0x25||RX_SEN||This register is setting RX Sensitivity level.||Go|
Complex bit access types are encoded to fit into small table cells. Table 3 shows the codes that are used for access types in this section.
|Set or cleared by hardware
|Reset or Default Value|
|-n||Value after reset or the default value|