The UCC14240-Q1 integrated isolated power solution
simplifies system design and reduces board area usage. Follow these guidelines for
proper PCB layout to achieve optimum performance.
- Place decoupling capacitors as close as possible to the device pins. For the input supply, place the capacitors between pins 6, 7 (VIN) and pins 1, 2, 5, 8–18 (GNDP). For the isolated output supply, place the capacitors between pin 28, 29 (VDD) and pins 19–25, 30–31, 35–36 (VEE). This location is of particular importance to the input decoupling capacitor because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits.
- Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on GNDP and VEE pins for best heat-sinking.
- If space and layer count allow, TI recommends to
connect the VIN, GNDP, VDD, and VEE pins to internal ground or power planes
through multiple vias. Alternatively, make the traces that are connected to
these pins as wide as possible to minimize losses.
- Minimize capacitive coupling between the RLIM pin
and the FBVEE pin by separating the traces while routing, and if possible use a
via near the FBVEE pin to route the feedback connection through a different
- A minimum of four layers is recommended to accomplish a good thermal PCB design. Inner layers can be used to create a high-frequency bypass capacitor between GNDP and VEE, which in turn mitigates radiated emissions.
- Pay close attention to the spacing between
primary ground plane (GNDP) and secondary ground plane (VEE) on the outer
layers of the PCB. The effective creepage and or clearance of the system will be
reduced if the two ground planes have a lower spacing than that of the
- To ensure isolation performance between the
primary and secondary side, avoid placing any PCB traces or copper below the