JAJSMY4 September   2021 UCC14240-Q1

ADVANCE INFORMATION  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Ratings
    6. 6.6 Insulation Specifications
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
      2. 7.3.2 Digital I/O ENA and /PG
      3. 7.3.3 Power-Up and Power-Down Sequencing
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RLIM Resistor Selection
        2. 8.2.2.2 Capacitor Selection
    3. 8.3 System Examples
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
  • DWN|36
サーマルパッド・メカニカル・データ
発注情報

RLIM Resistor Selection

The RLIM resistor chosen can provide enough current for the load using the following equations, whichever has lower RLIM value. Equation 1 shows source current due to capacitor variation and IQ. Equation 2 shows sink current due to capacitor variation and IQ.

Equation 1. R L I M _ M A X = V D D - C O M C O U T 3 × 1   -   C O U T 3 C O U T 2 × 1   -   C O U T 2   +   C O U T 3 × 1   -   C O U T 3   -   C O U T 3 C O U T 2   +   C O U T 3 × Q g t o t × f S W   +   I Q _ D R I V E R _ V E E   -   I Q _ D R I V E R _ V D D   - R L I M _ I N T
Equation 2. R L I M _ M A X = V E E - C O M C O U T 2 × 1   -   C O U T 2 C O U T 2 × 1   -   C O U T 2   +   C O U T 3 × 1   -   C O U T 3   -   C O U T 2 C O U T 2   +   C O U T 3 × Q g t o t × f S W   +   I Q _ D R I V E R _ V E E   -   I Q _ D R I V E R _ V D D   -   R L I M _ I N T

where

  • Qgtot is the total gate charge of power switch.
  • fSW is the switching frequency of gate drive load.
  • IQ_DRIVER_VDD is the maximum quiescent current of the gate driver from (VDD – COM), and any current pulled from VDD by external logic must be included.
  • IQ_DRIVER_VEE is the maximum quiescent current of the gate driver from (COM – VEE), and any current pulled from VEE by external logic must be included.

RLIM value determines response time of (COM – VEE) regulation. Too low an RLIM value can cause oscillation and can overload (VDD – VEE). Too high an RLIM value can give offset errors, due to slow response. If RLIM is greater than above calculations, then there is not enough current available to replenish the charge to the output capacitors, causing a charge imbalance where the voltage is not able to maintain regulation, and eventually exceeds the OVP2 or UVP2 FAULT thresholds and shutting down the device for protection.