The RLIM resistor chosen
can provide enough current for the load using the following equations, whichever has
lower RLIM value. Equation 1 shows source current due to capacitor variation and IQ. Equation 2 shows sink current due to capacitor variation and IQ.
- Qgtot is the total
gate charge of power switch.
- fSW is the switching
frequency of gate drive load.
- IQ_DRIVER_VDD is the
maximum quiescent current of the gate driver from (VDD – COM), and any current
pulled from VDD by external logic must be included.
- IQ_DRIVER_VEE is the
maximum quiescent current of the gate driver from (COM – VEE), and any current
pulled from VEE by external logic must be included.
RLIM value determines
response time of (COM – VEE) regulation. Too low an RLIM value can cause
oscillation and can overload (VDD – VEE). Too high an RLIM value can give
offset errors, due to slow response. If RLIM is greater than above
calculations, then there is not enough current available to replenish the charge to
the output capacitors, causing a charge imbalance where the voltage is not able to
maintain regulation, and eventually exceeds the OVP2 or UVP2 FAULT thresholds and
shutting down the device for protection.