SLUSDS3 March   2020 UCC21739-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
    1.     Pin Configuration and Functions
      1. Table 1. Pin Functions
  5. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  6. Parameter Measurement Information
    1. 6.1 Propagation Delay
      1. 6.1.1 Regular Turn-OFF
    2. 6.2 Input Deglitch Filter
    3. 6.3 Active Miller Clamp
      1. 6.3.1 External Active Miller Clamp
    4. 6.4 Under Voltage Lockout (UVLO)
      1. 6.4.1 VCC UVLO
      2. 6.4.2 VDD UVLO
    5. 6.5 OC (Over Current) Protection
      1. 6.5.1 OC Protection with 2-Level Turn-OFF
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply
      2. 7.3.2  Driver Stage
      3. 7.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 7.3.4  Active Pulldown
      5. 7.3.5  Short Circuit Clamping
      6. 7.3.6  External Active Miller Clamp
      7. 7.3.7  Overcurrent and Short Circuit Protection
      8. 7.3.8  2-Level Turn-off
      9. 7.3.9  Fault (FLT, Reset and Enable (RST/EN)
      10. 7.3.10 Isolated Analog to PWM Signal Function
    4. 7.4 Device Functional Modes
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input filters for IN+, IN- and RST/EN
        2. 8.2.2.2 PWM Interlock of IN+ and IN-
        3. 8.2.2.3 FLT, RDY and RST/EN Pin Circuitry
        4. 8.2.2.4 RST/EN Pin Control
        5. 8.2.2.5 Turn on and turn off gate resistors
        6. 8.2.2.6 External Active Miller Clamp
        7. 8.2.2.7 Overcurrent and Short Circuit Protection
          1. 8.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET
          2. 8.2.2.7.2 Protection Based on Desaturation Circuit
          3. 8.2.2.7.3 Protection Based on Shunt Resistor in Power Loop
        8. 8.2.2.8 Isolated Analog Signal Sensing
          1. 8.2.2.8.1 Isolated Temperature Sensing
          2. 8.2.2.8.2 Isolated DC Bus Voltage Sensing
        9. 8.2.2.9 Higher Output Current Using an External Current Buffer
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Turn on and turn off gate resistors

UCC21739-Q1 features split outputs OUTH and OUTL, which enables the independent control of the turn on and turn off switching speed. The turn on and turn off resistance determine the peak source and sink current, which controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver should be considered to ensure the device is in the thermal limit. At first, the peak source and sink current are calculated as:

Equation 1. UCC21739-Q1 eq-01-peak-current.gif

Where

  • ROH_EFF is the effective internal pull up resistance of the hybrid pull-up structure, shown in Figure 39, which is approximately 2 x ROL, about 0.7 Ω. This is the dominant resistance during the switching transient of the pull up structure.
  • ROL is the internal pulldown resistance, about 0.3 Ω
  • RON is the external turn on gate resistance
  • ROFF is the external turn off gate resistance
  • RG_Int is the internal resistance of the SiC MOSFET or IGBT module
UCC21739-Q1 Output-model-for-peak-gate-current_general.gifFigure 50. Output Model for Calculating Peak Gate Current

For example, for an IGBT module based system with the following parameters:

  • Qg = 3300 nC
  • RG_Int = 1.7 Ω
  • RON=ROFF= 1 Ω

The peak source and sink current in this case are:

Equation 2. UCC21739-Q1 eq-02-current-calcualtion.gif

Thus by using 1Ω external gate resistance, the peak source current is 5.9A, the peak sink current is 6.7A. The collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the miller plateau voltage. The hybrid pullup structure ensures the peak source current at the miller plateau voltage, unless the turn on gate resistor is too high. The faster the collector-to-emitter, Vce, voltage rises to VDC, the smaller the turn on switching loss is. The dV/dt can be estimated as Qgc/Isource_pk. For the turn off switching transient, the drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After Vce reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled by Vge. The peak sink current determines the dI/dt, which dominates the Vce voltage overshoot accordingly. If using relatively large turn off gate resistance, the Vce overshoot can be limited. The overshoot can be estimated by:

Equation 3. UCC21739-Q1 eq-03-delta-VCE.gif

Where

  • Lstray is the stray inductance in power switching loop, as shown in Figure 51
  • Iload is the load current, which is the turn off current of the power semiconductor
  • Cies is the input capacitance of the power semiconductor
  • Vplat is the plateau voltage of the power semiconductor
  • Vth is the threshold voltage of the power semiconductor
UCC21739-Q1 DPT-test-with-parasitics_general.gifFigure 51. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:

Equation 4. UCC21739-Q1 eq-04-driver-loss-1.gif

PQ is the quiescent power loss for the driver, which is Iq x (VDD-VEE) = 5mA x 20V = 0.100W. The quiescent power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic circuits, protection circuits when the driver is swithing when the driver is biased with VDD and VEE, and also the charging and discharing current of the internal circuit when the driver is switching. The power dissipation when the driver is switching can be calculated as:

Equation 5. UCC21739-Q1 eq-05-driver-loss2.gif

Where

  • Qg is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD
  • fsw is the switching frequency

In this example, the PSW can be calculated as:

Equation 6. UCC21739-Q1 eq-06-driver-loss-3.gif

Thus, the total power loss is:

Equation 7. UCC21739-Q1 eq-07-driver-loss-4.gif

When the board temperature is 125°C, the junction temperature can be estimated as:

Equation 8. UCC21739-Q1 eq-08-junction-temp.gif

Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency is ~50kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing external gate resistance, the gate driver can be operated at a higher switching frequency.