SLUSDS3 March   2020 UCC21739-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
    1.     Pin Configuration and Functions
      1. Table 1. Pin Functions
  5. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  6. Parameter Measurement Information
    1. 6.1 Propagation Delay
      1. 6.1.1 Regular Turn-OFF
    2. 6.2 Input Deglitch Filter
    3. 6.3 Active Miller Clamp
      1. 6.3.1 External Active Miller Clamp
    4. 6.4 Under Voltage Lockout (UVLO)
      1. 6.4.1 VCC UVLO
      2. 6.4.2 VDD UVLO
    5. 6.5 OC (Over Current) Protection
      1. 6.5.1 OC Protection with 2-Level Turn-OFF
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply
      2. 7.3.2  Driver Stage
      3. 7.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 7.3.4  Active Pulldown
      5. 7.3.5  Short Circuit Clamping
      6. 7.3.6  External Active Miller Clamp
      7. 7.3.7  Overcurrent and Short Circuit Protection
      8. 7.3.8  2-Level Turn-off
      9. 7.3.9  Fault (FLT, Reset and Enable (RST/EN)
      10. 7.3.10 Isolated Analog to PWM Signal Function
    4. 7.4 Device Functional Modes
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input filters for IN+, IN- and RST/EN
        2. 8.2.2.2 PWM Interlock of IN+ and IN-
        3. 8.2.2.3 FLT, RDY and RST/EN Pin Circuitry
        4. 8.2.2.4 RST/EN Pin Control
        5. 8.2.2.5 Turn on and turn off gate resistors
        6. 8.2.2.6 External Active Miller Clamp
        7. 8.2.2.7 Overcurrent and Short Circuit Protection
          1. 8.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET
          2. 8.2.2.7.2 Protection Based on Desaturation Circuit
          3. 8.2.2.7.3 Protection Based on Shunt Resistor in Power Loop
        8. 8.2.2.8 Isolated Analog Signal Sensing
          1. 8.2.2.8.1 Isolated Temperature Sensing
          2. 8.2.2.8.2 Isolated DC Bus Voltage Sensing
        9. 8.2.2.9 Higher Output Current Using an External Current Buffer
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics

UCC21739-Q1 D016.gifFigure 4. Output High Drive Current vs. Temperature
UCC21739-Q1 D017.gifFigure 5. Output Low Driver Current vs. Temperature
UCC21739-Q1 D015.gif
IN+ = High IN- = Low
Figure 6. IVCCQ Supply Current vs. Temperature
UCC21739-Q1 D014.gif
IN+ = Low IN- = Low
Figure 7. IVCCQ Supply Current vs. Temperature
UCC21739-Q1 D018.gifFigure 8. IVCCQ Supply Current vs. Input Frequency
UCC21739-Q1 D012.gif
IN+ = High IN- = Low
Figure 9. IVDDQ Supply Current vs. Temperature
UCC21739-Q1 D013.gif
IN+ = Low IN- = Low
Figure 10. IVDDQ Supply Current vs. Temperature
UCC21739-Q1 D019.gif
Figure 11. IVDDQ Supply Current vs. Input Frequency
UCC21739-Q1 D001.gifFigure 12. VCC UVLO vs. Temperature
UCC21739-Q1 D002.gifFigure 13. VDD UVLO vs. Temperature
UCC21739-Q1 D021.gif
VCC = 3.3V VDD=18V CL = 100pF
RON = 0Ω ROFF = 0Ω
Figure 14. Propagation Delay tPDLH vs. Temperature
UCC21739-Q1 D022.gif
VCC = 3.3V VDD=18V CL = 100pF
RON = 0Ω ROFF = 0Ω
Figure 15. Propagation Delay tPDHL vs. Temperature
UCC21739-Q1 D023.gif
VCC = 3.3V VDD=18V CL = 10nF
RON = 0Ω ROFF = 0Ω
Figure 16. tr Rise Time vs. Temperature
UCC21739-Q1 D024.gif
VCC = 3.3V VDD=18V CL = 10nF
RON = 0Ω ROFF = 0Ω
Figure 17. tf Fall Time vs. Temperature
UCC21739-Q1 D008.gifFigure 18. VOUTPD Output Active Pulldown Voltage vs. Temperature
UCC21739-Q1 D025.gif
Figure 19. VCLP-OUT(H) Short Circuit Clamping Voltage vs. Temperature
UCC21739-Q1 D026.gif
Figure 20. VCLP-OUT(L) Short Circuit Clamping Voltage vs. Temperature
UCC21739-Q1 D009.gifFigure 21. VCLMPTH Miller Clamp Threshold Voltage vs. Temperature
UCC21739-Q1 D010.gif
Figure 22. ICLMPEL Miller Clamp Sink Current vs. Temperature
UCC21739-Q1 D011.gif
Figure 23. tDCLMPE Miller Clamp ON Delay Time vs. Temperature
UCC21739-Q1 D020.gif
Figure 24. tOCOFF OC Propagation Delay vs. Temperature
UCC21739-Q1 D003.gif
Figure 25. VOCTH OC Detection Threshold vs. Temperature
UCC21739-Q1 D004.gif
Figure 26. tOCFLT OC to FLT Low Delay Time vs. Temperature
UCC21739-Q1 D005.gif
Figure 27. V2LOFF 2-Level Turn Off Voltage Threshold vs. Temperature
UCC21739-Q1 D006.gif
Figure 28. t2LOFF 2-Level Turn Off Time vs. Temperature