SLUSBE8B May   2013  – September 2015 UCC28720

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Primary-Side Voltage Regulation
      2. 7.4.2 Primary-Side Current Regulation
      3. 7.4.3 Valley Switching
      4. 7.4.4 Start-Up Operation
      5. 7.4.5 Fault Protection
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stand-by Power Estimate
        2. 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
        3. 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. 8.2.2.4 Transformer Parameter Verification
        5. 8.2.2.5 Output Capacitance
        6. 8.2.2.6 VDD Capacitance, CDD
        7. 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Terms
          1. 11.1.1.1.1  Capacitance Terms in Farads
          2. 11.1.1.1.2  Duty Cycle Terms
          3. 11.1.1.1.3  Frequency Terms in Hertz
          4. 11.1.1.1.4  Current Terms in Amperes
          5. 11.1.1.1.5  Current and Voltage Scaling Terms
          6. 11.1.1.1.6  Transformer Terms
          7. 11.1.1.1.7  Power Terms in Watts
          8. 11.1.1.1.8  Resistance Terms in Ω
          9. 11.1.1.1.9  Timing Terms in Seconds
          10. 11.1.1.1.10 Voltage Terms in Volts
          11. 11.1.1.1.11 AC Voltage Terms in VRMS
          12. 11.1.1.1.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

The UCC28720 is a flyback power supply controller which provides accurate voltage and constant current regulation with primary-side feedback, eliminating the need for opto-coupler feedback circuits. The controller operates in discontinuous conduction mode with valley-switching to minimize switching losses. The modulation scheme is a combination of frequency and primary peak current modulation to provide high conversion efficiency across the load range. The control law provides a wide-dynamic operating range of output power which allows the power designer to achieve the <10-mW stand-by power requirement.

During low-power operating ranges the device has power management features to reduce the device operating current at operating frequencies below 28 kHz. Accurate voltage and constant current regulation, fast dynamic response, and fault protection are achieved with primary-side control. A complete charger solution can be realized with a straightforward design process, low cost and low component count.

7.2 Functional Block Diagram

UCC28720 block_v13094_lusbe8.gif

7.3 Feature Description

7.3.1 Detailed Pin Description

VDD (Device Bias Voltage Supply): The VDD pin is connected to a bypass capacitor to ground. The VDD turn-on UVLO threshold is 21 V and turn-off UVLO threshold is 8.1 V, with an available operating range up to 35 V on VDD. The USB charging specification requires the output current to operate in constant-current mode from 5 V to a minimum of 2 V; this is easily achieved with a nominal VDD of approximately 25 V. The additional VDD headroom up to 35 V allows for VDD to rise due to the leakage energy delivered to the VDD capacitor in high-load conditions.

GND (Ground): There is a single ground reference external to the device for the base drive current and analog signal reference. Place the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on the VS and CS signal pins.

HV (High Voltage Start-up): The HV pin is connected directly to the bulk capacitor to provide start-up current to the VDD capacitor. The typical start-up current is ~300 µA which provides fast charging of the VDD capacitor. The internal HV start-up device is active until VDD exceeds the turn-on UVLO threshold at which time the HV start-up device is turned off. In the off state the leakage current is very low to minimize standby losses of the controller. When VDD falls below the UVLO turn-off threshold the HV start-up device is turned on.

VS (Voltage-Sense): The VS pin is connected to a resistor divider from the auxiliary winding to ground. The output-voltage feedback information is sampled at the end of the transformer secondary current demagnetization time to provide an accurate representation of the output voltage. Timing information to achieve valley-switching and to control the duty cycle of the secondary transformer current is determined by the waveform on the VS pin. Avoid placing a filter capacitor on this input which would interfere with accurate sensing of this waveform.

The VS pin also senses the bulk capacitor voltage to provide for AC-input run and stop thresholds, and to compensate the current-sense threshold across the AC-input range. During the transistor on-time the VS pin is clamped to approximately 250 mV below GND and the current out of the VS pin is sensed. For the AC-input run/stop function, the run threshold on VS is 225 µA and the stop threshold is 80 µA. The values for the auxilliary voltage divider upper-resistor RS1 and lower-resistor RS2 can be determined by the equations below.

Equation 1. UCC28720 q_dp_Rs1_lusb41.gif

where

  • NPA is the transformer primary-to-auxiliary turns ratio,
  • VIN(run) is the AC RMS voltage to enable turn-on of the controller (run),
  • IVSL(run) is the run-threshold for the current pulled out of the VS pin during the switch on-time. (see Electrical Characteristics)
Equation 2. UCC28720 qu3_lusb86.gif

where

  • VOCV is the converter regulated output voltage,
  • VF is the output rectifier forward drop at near-zero current,
  • NAS is the transformer auxiliary to secondary turns ratio,
  • RS1 is the VS divider high-side resistance,
  • VVSR is the CV regulating level at the VS input (see Electrical Characteristics).

DRV (Base Drive): The DRV pin is connected to the NPN transistor base pin. The driver provides a base drive signal limited to 7 V. The turn-on characteristic of the driver is a 15 mA to 35-mA current source that is scaled with the current sense threshold dictated by the operating point in the control scheme. When the minimum current sense threshold is being used, the base drive current is also at its minimum value. As the current sense threshold is increased to the maximum, the base drive current scales linearly with it to its maximum of 35 mA typical. The turn-off current is determined by the low-side driver RDS(on)

CS (Current Sense): The current-sense pin is connected through a series resistor (RLC) to the current-sense resistor (RCS). The current-sense threshold is 0.78 V for IPP(max) and 0.195 V for IPP(min). The series resistor RLC provides the function of feed-forward line compensation to eliminate change in IPP due to change in di/dt and the propagation delay of the internal comparator and NPN transistor turn-off time. There is an internal leading-edge blanking time of approximately 300 ns to eliminate sensitivity to the turn-on current spike. It should not be necessary to place a bypass capacitor on the CS pin. The value of RCS is determined by the target output current in Constant Current (CC) regulation. The values of RCS and RLC can be determined by the equations below. The term ηXFMR is intended to account for the energy stored in the transformer but not delivered to the secondary. This includes transformer resistance and core loss, bias power, and primary-to-secondary leakage ratio.

Example: With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%, and bias power to output power ratio of 1.5%. The ηXFMR value is approximately: 1 - 0.05 - 0.035 - 0.015 = 0.9.

Equation 3. UCC28720 qu2_lusb86.gif

where

  • VCCR is a current regulation constant (see Electrical Characteristics),
  • NPS is the transformer primary-to-secondary turns ratio (a ratio of 13 to 15 is recommended for 5-V output),
  • IOCC is the target output current in constant-current regulation,
  • ηXFMR is the transformer efficiency.
Equation 4. UCC28720 q_rlc_lusb88.gif

where

  • RS1 is the VS pin high-side resistor value,
  • RCS is the current-sense resistor value,
  • t D is the current-sense delay including NPN transistor turn-off delay, add ~50 ns to transistor delay,
  • NPA is the transformer primary-to-auxiliary turns ratio,
  • LP is the transformer primary inductance,
  • KLC is a current-scaling constant (see Electrical Characteristics).

CBC (Cable Compensation): The cable compensation pin is connected to a resistor to ground to program the amount of output voltage compensation to offset cable resistance. The cable compensation block provides a 0-V to 3-V voltage level on the CBC pin corresponding to IOCC(max) output current. Connecting a resistance from CBC to GND programs a current that is summed into the VS feedback divider, increasing the regulation voltage as IOUT increases. There is an internal series resistance of 28 kΩ to the CBC pin which sets a maximum cable compensation of a 5-V output to 400 mV when CBC is shorted to ground. The CBC resistance value can be determined by the equation below.

Equation 5. UCC28720 q_dp_Rcbc_lusb41.gif

where

  • VOCV is the regulated output voltage,
  • VF is the diode forward voltage in V,
  • VOCBC is the target cable compensation voltage at the output terminals,
  • VCBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current (see Electrical Characteristics),
  • VVSR is the CV regulating level at the VS input (see Electrical Characteristics).

7.4 Device Functional Modes

7.4.1 Primary-Side Voltage Regulation

Figure 13 illustrates a simplified flyback convertor with the main voltage regulation blocks of the device shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary-side control.

UCC28720 fly_v13093_lusbe8.gif Figure 13. Simplified Flyback Convertor
(with the Main Voltage Regulation Blocks)

In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer energy to the secondary. As shown in Figure 14 it is clear there is a down slope representing a decreasing total rectifier VF and resistance voltage drop (ISRS) as the secondary current decreases to zero. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably recognizes the leakage inductance reset and ringing and ingores it, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current. The internal reference on VS is 4.05 V. Temperature compensation on the VS reference voltage of -0.8-mV/°C offsets the change in the output rectifier forward voltage with temperature. The resistor divider is selected as outlined in the VS pin description.

UCC28720 ai_aux-winding-v_lusb41.gif Figure 14. Auxiliary Winding Voltage

The UCC28720 includes a VS signal sampler that uses discrimination methods to ensure an accurate sample of the output voltage from the auxiliary winding. There are some conditions that must be met on the auxiliary winding signal to ensure reliable operation. These conditions are the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 15 below for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset pedestal, tLK_RESET in Figure 15. Because this can mimic the waveform of the secondary current decay, followed by a sharp downslope, it is important to keep the leakage reset time less than 600 ns for IPRI minimum, and less than 2.2 µs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX waveform following tLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 100 mVp-p at least 200 ns before the end of the demagnetization time, tDM. If there is a concern with excessive ringing, it usually occurs during light or no-load conditions, when tDM is at the minimum. The tolerable ripple on VS scales up when measured at the auxiliary winding by RS1 and RS2, and is equal to 100 mV x (RS1 + RS2) / RS2 when measured directly at the auxilliary winding.

UCC28720 v12202_lusb88.gif Figure 15. Auxiliary Waveform Details

During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode as illustrated in Figure 16 below. The internal operating frequency limits of the device are 80 kHz, fSW(max) and 65 Hz, fSW(min). The transformer primary inductance and primary peak current chosen sets the maximum operating frequency of the converter. The output preload resistor and efficiency at low power determines the converter minimum operating frequency. There is no stability compensation required for the UCC28720.

UCC28720 control_law_v13095_lusbe8.gif Figure 16. Frequency and Amplitude Modulation Modes
(during Voltage Regulation)

7.4.2 Primary-Side Current Regulation

Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary average current. The control law dictates that as power is increased in CV regulation and approaching CC regulation the primary-peak current is at IPP(max). Referring to Figure 17 below, the primary-peak current, turns ratio, secondary demagnetization time (tDM), and switching period (tSW) determine the secondary average output current. Ignoring leakage inductance effects, the average output current is given by Equation 6. When the average output current reaches the regulation reference in the current control block, the controller operates in frequency modulation mode to control the output current at any output voltage at or below the voltage regulation target as long as the auxiliary winding can keep VDD above the UVLO turn-off threshold.

UCC28720 v12203_lusb88.gif Figure 17. Transformer Currents
Equation 6. UCC28720 q_iout_lusb88.gif
UCC28720 v12201_lusb88.gif Figure 18. Typical Target Output V-I Characteristic

7.4.3 Valley Switching

The UCC28720 utilizes valley switching to reduce switching losses in the transistor, to reduce induced-EMI, and to minimize the turn-on current spike at the sense resistor. The controller operates in valley-switching in all load conditions unless the collector voltage (VC) ringing has subsided.

Referring to Figure 19 below, the UCC28720 operates in a valley-skipping mode in most load conditions to maintain an accurate voltage or current regulation point and still switch on the lowest available VC.

UCC28720 valley_v13091_lusbe8.gif Figure 19. Valley-Skipping Mode

7.4.4 Start-Up Operation

The internal high-voltage start-up switch connected to the bulk capacitor voltage (VBLK) through the HV pin charges the VDD capacitor. During start up there is typically 300 µA available to charge the VDD capacitor. When VDD reaches the 21-V UVLO turn-on threshold, the controller is enabled, the converter starts switching and the start-up switch is turned off. The initial three cycles are limited to IPP(min). After the initial three cycles at minimum IPP(min), the controller responds to the condition dictated by the control law. The converter will remain in discontinuous mode during charging of the output capacitor(s), maintaining a constant output current until the output voltage is in regulation.

7.4.5 Fault Protection

The UCC28720 provides comprehensive fault protection. Protection functions include:

  • Output over-voltage fault
  • Input under-voltage fault
  • Internal over-temperature fault
  • Primary over-current fault
  • CS pin fault
  • VS pin fault

A UVLO reset and restart sequence applies for all fault protection events.

The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on VS exceeds 115% of the nominal VOUT, the device stops switching and the internal current consumption is IFAULT which discharges the VDD capacitor to the UVLO turn-off threshold. After that, the device returns to the start state and a start-up sequence ensues.

The UCC28720 always operates with cycle-by-cycle primary peak current control. The normal operating range of the CS pin is 0.78 V to 0.195 V. There is additional protection if the CS pin reaches 1.5 V. This results in a UVLO reset and restart sequence.

The line input run and stop thresholds are determined by current information at the VS pin during the transistor on-time. While the VS pin is clamped close to GND during the transistor on-time, the current through RS1 is monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and stop thresholds allows clean start-up and shut-down of the power supply with the line voltage. The run current threshold is 225 µA and the stop current threshold is 80 µA.

The internal over-temperature protection threshold is 165°C. If the junction temperature reaches this threshold the device initiates a UVLO reset cycle. If the temperature is still high at the end of the UVLO cycle, the protection cycle repeats.

Protection is included in the event of component failures on the VS pin. If complete loss of feedback information on the VS pin occurs, the controller stops switching and restarts.