JAJSE40A October 2017 – February 2018 UCC28780
The HVG pin provides a controlled voltage to the gate of the depletion-mode MOSFET (QS), enabling QS to serve both VVDD startup and lossless ZVS sensing from the high-voltage switch node (VSW). During VVDD startup, the UVLO circuit commands two power-path switches connecting SWS and HVG pins to VDD pin with two internal current-limit resistors (RDDS and RDDH) separately, as shown in Figure 16. In this configuration, QS behaves as a current source to charge the VDD capacitor (CVDD). RDDS is set at 12 kΩ when VVDD is below 1 V to limit the maximum fault current under VDD pin short events. RDDS is reduced to 1 kΩ when VVDD rises above 1 V to allow VVDD to charge faster. The maximum charge current (ISWS) is affected by RDDS, the external series resistance (RSWS) from SWS pin to QS, and the threshold voltage of QS (VTH(Qs)). ISWS can be calculated as
After VVDD reaches VVDD(ON), the two power-path switches open the connections among SWS, HVG, and VDD pins. At this point, a third power-path switch connects an internal 11-V regulator to the HVG pin for configuring QS to perform lossless ZVS sensing. As QS gate is fixed at 11 V and the drain pin voltage of QS becomes higher than the sum of QS threshold voltage (VTH(Qs)) and the 11-V gate voltage, QS turns off and the source pin voltage of QS can no longer follow the drain pin voltage change, so this gate control method makes QS act as a high-voltage blocking device with the drain pin connected to VSW. When the controller is switching, VSW can be lower than 11 V, so QS turns on and forces the source pin voltage to follow VSW, becoming a replica of the VSW waveform at the lower voltage level, as illustrated in Figure 17.
The limited window for monitoring the VSW waveform suffices for ZVS control of the UCC28780, since the ZVS tuning threshold (VTH(SWS)) is lower than that, which is at 9 V for VSET = 5 V and at 4 V for VSET = 0 V. The 9-V threshold is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial ZVS condition on the ACF using Si primary switches. On the other hand, performing full ZVS operation is more suitable for the ACF with GaN primary switches. The 4-V threshold can help to better compensate sensing delay between VSW and the SWS pin more than using a 0-V threshold. The internal 11-V regulator requires a high quality ceramic bypass capacitor (CHVG) between the HVG pin and GND for noise filtering and providing compensation to the regulator circuitry. The minimum CHVG value is 2.2 nF and an X7R-type dielectric capacitor is recommended. The controller enters a fault state if the HVG pin is open or shorted to GND during VVDD start-up, or if VHVG overshoot is higher than VHVG(OV) of 13.8 V in run state. The output short current of HVG regulator (IS(HVG)) is self-limited to around 1mA.