JAJSE40A October 2017 – February 2018 UCC28780
The RUN pin is a logic-level output signal to enable the gate driver. It generates a 5-V logic output when the driver should be active, and pulls down to less than 0.5 V when the driver should be disabled. During burst mode operation, the RUN pin serves as a power management function to dynamically reduce the static current of the driver, so light-load efficiency can be further improved and standby power can be minimized. In addition, there are two delays between RUN going high to first PWML pulse going high in each burst packet. The first delay is a fixed 2.2-μs delay time, intended to provide an appropriate wake-up time for UCC28780 and the gate driver to transition from a wait state to a run state. The second delay is another 2.2-μs timeout, tZC in the electrical table, intended to turn on the low-side switch of the first switching cycle per burst packet around the valley point of DCM ringing by waiting for the zero crossing detection (ZCD) on the auxiliary winding voltage (VAUX). Therefore, the minimum total delay time is 2.2 μs typically if ZCD is detected immediately after the first 2.2-μs wake-up time, while the maximum total delay time is 4.4 μs if ZCD is not triggered after the timeout. The total delay time with tolerance over temperature are listed as tD(RUN-PWML) in the electrical table. RUN pin can also be used to control the external active ripple compensation network to enhance the stability of the burst regulation loop.