JAJSE40A October 2017 – February 2018 UCC28780
When an output short-circuit is applied, the peak current reaches the PCL limit and triggers the 160-ms OPP fault timer. During this event, the VDD power supply is lost due to the auxiliary winding voltage being close to 0 V. Without additional short-circuit detection, if VVDD reaches VVDD(OFF) before the 160-ms timeout, the 1.5-s recovery time for the OPP fault cannot be triggered but only a UVLO recycle is performed. To remedy this scenario, as VVDD reaches VVDD(OFF), UCC28780 checks two additional parameters to identify the short-circuit event at the output, and initiates the 1.5-s recovery without waiting for 160 ms to expire. Specifically, when VVDD reaches VVDD(OFF), if either VCST is greater than the OPP threshold (VCST(OPP)) or the VS-pin voltage is less than 0.6 V, the 1.5-s recovery delay is initiated. With this additional layer of intelligence, the average load current during continued short-circuit event can be greatly reduced, and thus also the thermal stress on the power supply.