JAJSE40A October 2017 – February 2018 UCC28780
As shown in Figure 30, after VVDD reaches VVDD(ON), an internal 11-V regulator on the HVG pin should force VHVG back to the regulation level before PWML starts switching. If the recommended HVG-pin capacitor (CHVG) of 2.2 nF and the connection to the depletion-mode MOSFET (QS) are in place, the settling time of VHVG to 11 V is much longer than 10 μs with a limited sink current of the regulator (ISE(HVG)) to discharge CHVG.
The first fault scenario is that if CHVG is too small, or the HVG pin is open, the pin is not able to control QS correctly for the high-voltage sensing function of ZVS control, so no switching action will be performed. When either two situations happen, VHVG settles to 11 V very quickly instead. Therefore, after a 10-μs delay from the instance of VVDD reaching VVDD(ON), UCC28780 checks if VHVG is below 12 V for the pin-fault detection, and then performs one UVLO cycle of VDD directly without switching as the protection response. The above protection is to prevent the controller from generating PWM signals. However, when the HVG pin is open and disconnected from the QS gate, the source voltage of QS keeps increasing until the TVS on the SWS pin (DSWS) starts to clamp the voltage continuously. To shrink the size of DSWS without incurring too much thermal stress in the small package in this fault condition, it is highly recommended that a small Zener diode (DHVG) between QS gate to ground should be used to limit the QS source voltage. Same as DSWS, DHVG should be higher than VVDD(ON), so as to prevent interference with normal VDD startup.
The second fault scenario is the over-voltage condition of HVG pin after the converter starts switching. When the switch-node voltage (VSW) rises with a high dV/dt condition, there is a charge current flowing through the junction capacitance of QS, and part of the current can charge up CHVG. If the overshoot is too large, the voltage on the SWS pin also increases due to the nature of the depletion-mode MOSFET operation. UCC28780 detects the overshoot event on HVG pin with an over-voltage threshold (VHVG(OV)) of 13.8V cycle-by-cycle. When VHVG is higher than VHVG(OV) for three consecutive PWML pulses, the HVG over-voltage protection is triggered which performs one UVLO cycle of VDD.
The third fault scenario is an HVG pin short event at the beginning of VDD startup, and QS is not able to charge up the VDD capacitor to VDD(ON), so there is no chance to enable the controller.