ADC12J4000 ADC12J4000 超広帯域 RF サンプリング・サブシステム | TIJ.co.jp

ADC12J4000
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ADC12J4000 超広帯域 RF サンプリング・サブシステム

ADC12J4000 超広帯域 RF サンプリング・サブシステム - ADC12J4000
データシート
 

概要

The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.

特長

  • Excellent Noise and Linearity up to and beyond FIN = 3 GHz
  • Configurable DDC
  • Decimation Factors from 4 to 32 (Complex Baseband Out)
  • Usable Output Bandwidth of 800 MHz at
    4x Decimation and 4000 MSPS
  • Usable Output Bandwidth of 100 MHz at
    32x Decimation and 4000 MSPS
  • Bypass Mode for Full Nyquist Output Bandwidth
  • Low Pin-Count JESD204B Subclass 1 Interface
  • Automatically Optimized Output Lane Count
  • Embedded Low Latency Signal Range Indication
  • Low Power Consumption
  • Key Specifications:
    • Max Sampling Rate: 4000 MSPS
    • Min Sampling Rate: 1000 MSPS
    • DDC Output Word Size: 15-Bit Complex (30 bits total)
    • Bypass Output Word Size: 12-Bit Offset Binary
    • Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz
    • IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS)
    • FPBW (–3 dB): 3.2 GHz
    • Peak NPR: 46 dB
    • Supply Voltages: 1.9 V and 1.2 V
    • Power Consumption
      • Bypass (4000 MSPS): 2 W
      • Decimate by 10 (4000 MSPS): 2 W
      • Power Down Mode: <50 mW

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機能一覧

他の製品と比較 高速 ADCs (>10MSPS) メール Excelへダウンロード
Part number オーダー・オプション Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADC12J4000 ご注文 4000     Ultra High Speed     12     1     55     8.8     71     2000     0.725     JESD204B     -40 to 85     3200     Yes     VQFN | 68     68VQFN: 100 mm2: 10 x 10 (VQFN | 68)     Catalog     Folding Interpolating    
ADC12J1600 サンプルは利用できません。 1600     Ultra High Speed     12     1     55.3     8.8     75     1600     0.725     JESD204B     -40 to 85     3200     Yes     VQFN | 68     68VQFN: 100 mm2: 10 x 10 (VQFN | 68)     Catalog     Folding Interpolating    
ADC12J2700 サンプルは利用できません。 2700     Ultra High Speed     12     1     55.1     8.8     72     1800     0.725     JESD204B     -40 to 85     3200     Yes     VQFN | 68     68VQFN: 100 mm2: 10 x 10 (VQFN | 68)     Catalog     Folding Interpolating