The 320C6201B DSP is a member of the fixed-point DSP family in the 320C6000 platform. The
SM/SMJ320C6201B (C6201B) device is based on the high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an
excellent choice for multichannel and multifunction applications. With performance of up to 1600 million
instructions per second (MIPS) at a clock rate of 200 MHz, the C6201B offers cost-effective solutions to
high-performance DSP programming challenges. The C6201B is a newer revision of the C6201. The C6201B
DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array
processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent
functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of
parallelism and two 16-bit multipliers for a 32-bit result. The C6201B can produce two multiply-accumulates
(MACs) per cycle - for a total of 400 million MACs per second (MMACS). The C6201B DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6201B includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.
Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program
space. Data memory of the C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The
peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a
host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM
or SBSRAM and asynchronous peripherals.
The C6201B has a complete set of development tools which includes: a new C compiler, a third-party Ada 95
compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface
for visibility into source code execution.