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SN65LVDS32B

アクティブ

-2 ~ 4.4V の同相電圧範囲、クワッド LVDS レシーバ

製品詳細

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard for Signaling Rates(1) up to 400 Mbps
  • Operates With a Single 3.3-V Supply
  • -2-V to 4.4-V Common-Mode Input Voltage Range
  • Differential Input Thresholds <50 mV With 50 mV of Hysteresis Over Entire Common-
    Mode Input Voltage Range
  • Integrated 110- Line Termination Resistors Offered With the LVDT Series
  • Propagation Delay Times 4 ns (typ)
  • Active Fail Safe Assures a High-Level Output With No Input
  • Bus-Pin ESD Protection Exceeds 15 kV—HBM
  • Inputs Remain High-Impedance on Power Down
  • Recommended Maximum Parallel Rate of 200 M-Transfer/s
  • Available in Small-Outline Package With 1,27-mm Terminal Pitch
  • Pin-Compatible With the AM26LS32, MC3486, or µA9637

(1) Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bit/s (bits per second).

  • Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard for Signaling Rates(1) up to 400 Mbps
  • Operates With a Single 3.3-V Supply
  • -2-V to 4.4-V Common-Mode Input Voltage Range
  • Differential Input Thresholds <50 mV With 50 mV of Hysteresis Over Entire Common-
    Mode Input Voltage Range
  • Integrated 110- Line Termination Resistors Offered With the LVDT Series
  • Propagation Delay Times 4 ns (typ)
  • Active Fail Safe Assures a High-Level Output With No Input
  • Bus-Pin ESD Protection Exceeds 15 kV—HBM
  • Inputs Remain High-Impedance on Power Down
  • Recommended Maximum Parallel Rate of 200 M-Transfer/s
  • Available in Small-Outline Package With 1,27-mm Terminal Pitch
  • Pin-Compatible With the AM26LS32, MC3486, or µA9637

(1) Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bit/s (bits per second).

This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers.

Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of -4 to 5 V in their SN65LVDS/T33 and SN65LVDS/T34.

Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling.

The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and SN65LVDT9637B are characterized for operation from -40°C to 85°C.

This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers.

Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of -4 to 5 V in their SN65LVDS/T33 and SN65LVDS/T34.

Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling.

The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and SN65LVDT9637B are characterized for operation from -40°C to 85°C.

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技術資料

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート High-Speed Differential Receivers データシート (Rev. B) 2007年 4月 23日
アプリケーション概要 LVDS to Improve EMC in Motor Drives 2018年 9月 27日
アプリケーション概要 How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
アプリケーション概要 How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日
アプリケーション・ノート Active Fail-Safe in TI's LVDS Receivers (Rev. B) 2001年 10月 31日

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価ボード

SN65LVDS31-32BEVM — SN65LVDS31-32B:LVDS31 と LVDS32B 向け LVDS (低電圧差動信号伝送) の評価基板

TI offers a series of low-voltage differential signaling (LVDS) evaluation modules (EVMs) designed for analysis of the electrical characteristics of LVDS drivers and receivers. Four unique EVMs are available to evaluate the different classes of LVDS devices offered by TI.

Combination Table

As seen (...)

ユーザー ガイド: PDF
シミュレーション・モデル

SN65LVDS32B IBIS Model

SLLC034.ZIP (4 KB) - IBIS Model
シミュレーション・ツール

PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®

PSpice® for TI は、各種アナログ回路の機能評価に役立つ、設計とシミュレーション向けの環境です。設計とシミュレーションに適したこのフル機能スイートは、Cadence® のアナログ分析エンジンを使用しています。PSpice for TI は無償で使用でき、アナログや電源に関する TI の製品ラインアップを対象とする、業界でも有数の大規模なモデル・ライブラリが付属しているほか、選択された一部のアナログ動作モデルも利用できます。

設計とシミュレーション向けの環境である PSpice for TI (...)
シミュレーション・ツール

TINA-TI — SPICE ベースのアナログ・シミュレーション・プログラム

TINA-TI は、DC 解析、過渡解析、周波数ドメイン解析など、SPICE の標準的な機能すべてを搭載しています。TINA には多彩な後処理機能があり、結果を必要なフォーマットにすることができます。仮想計測機能を使用すると、入力波形を選択し、回路ノードの電圧や波形を仮想的に測定することができます。TINA の回路キャプチャ機能は非常に直観的であり、「クイックスタート」を実現できます。

TINA-TI をインストールするには、約 500MB が必要です。インストールは簡単です。必要に応じてアンインストールも可能です。(そのようなことはないと思いますが)

TINA は DesignSoft (...)

ユーザー ガイド: PDF
英語版 (Rev.A): PDF
パッケージ ピン数 ダウンロード
SOIC (D) 16 オプションの表示

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 材質成分
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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