SN74LV221A

アクティブ

デュアル、モノステーブル・マルチバイブレータ

製品詳細

Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Technology family LV-A Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 12 IOH (max) (mA) -12 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Technology family LV-A Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 12 IOH (max) (mA) -12 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 11 ns at 5 V
  • Support Mixed-Mode Voltage Operation on All Ports
  • Schmitt-Trigger Circuitry on A\, B, and CLR\ Inputs for Slow Input Transition Rates
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 11 ns at 5 V
  • Support Mixed-Mode Voltage Operation on All Ports
  • Schmitt-Trigger Circuitry on A\, B, and CLR\ Inputs for Slow Input Transition Rates
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The ’LV221A devices are dual multivibrators designed for 2-V to 5.5-V VCC operation. Each multivibrator has a negative-transition-triggered (A\) input and a positive-transition-triggered (B) input, either of which can be used as an inhibit input.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A\ input is low and the B input goes high. In the second method, the B input is high and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR\) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistor between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low.

Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the outputs are independent of further transitions of the A\ and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering and clearing sequences are illustrated in the input/output timing diagram.

The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’LV221A is shown in Figure 8. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 5.

During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Pin assignments are identical to those of the ’AHC123A and ’AHCT123A devices, so the ’LV221A can be substituted for those devices not using the retrigger feature.

For additional application information on multivibrators, see the application report Designing With The SN74AHC123A and SN74AHCT123A, literature number SCLA014.

The ’LV221A devices are dual multivibrators designed for 2-V to 5.5-V VCC operation. Each multivibrator has a negative-transition-triggered (A\) input and a positive-transition-triggered (B) input, either of which can be used as an inhibit input.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A\ input is low and the B input goes high. In the second method, the B input is high and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR\) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistor between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low.

Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the outputs are independent of further transitions of the A\ and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering and clearing sequences are illustrated in the input/output timing diagram.

The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’LV221A is shown in Figure 8. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 5.

During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Pin assignments are identical to those of the ’AHC123A and ’AHCT123A devices, so the ’LV221A can be substituted for those devices not using the retrigger feature.

For additional application information on multivibrators, see the application report Designing With The SN74AHC123A and SN74AHCT123A, literature number SCLA014.

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SN74LV123A アクティブ デュアル、再トリガ可能、モノステーブル・マルチバイブレータ Voltage range (2V to 5.5V), average drive strength (12mA), average propagation delay (9ns)

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート SN54LV221A, SN74LV221A データシート (Rev. G) 2005年 4月 22日
製品概要 Configurable Timed Reset Using Discrete Logic (Rev. A) PDF | HTML 2023年 5月 2日
アプリケーション・ノート Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 2020年 3月 13日

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価ボード

14-24-LOGIC-EVM — 14 ピンから 24 ピンの D、DB、DGV、DW、DYY、NS、PW の各パッケージに封止した各種ロジック製品向けの汎用評価基板

14-24-logic-EVM 評価基板は、14 ピンから 24 ピンの D、DW、DB、NS、PW、DYY、DGV の各パッケージに封止した各種ロジック デバイスをサポートする設計を採用しています。

ユーザー ガイド: PDF | HTML
シミュレーション・モデル

HSPICE Model of SN74LV221A

SCEJ252.ZIP (89 KB) - HSpice Model
シミュレーション・モデル

SN74LV221A IBIS Model (Rev. A)

SCEM135A.ZIP (21 KB) - IBIS Model
パッケージ ピン数 ダウンロード
SOIC (D) 16 オプションの表示
SOP (NS) 16 オプションの表示
TSSOP (PW) 16 オプションの表示
TVSOP (DGV) 16 オプションの表示

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 材質成分
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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