SN74LVC1G132 シングル、 2入力 NAND ゲート、シュミットトリガ入力 | TIJ.co.jp

SN74LVC1G132
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シングル、 2入力 NAND ゲート、シュミットトリガ入力

 

概要

The SN74LVC1G132 device contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V VCC operation and performs the Boolean function Y = A × B or Y = A + B in positive logic.

Because of Schmitt action, this device has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

特長

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in Texas Instruments
    NanoStar™ and NanoFree™ Packages
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation

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機能一覧

他の製品と比較 NAND ゲート メール Excelへダウンロード
Part number オーダー・オプション Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Rating Data rate (Max) (Mbps) Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
SN74LVC1G132 ご注文 LVC     1.65     5.5     1     2     32     -32     Schmitt-Trigger     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
Catalog     100     -40 to 125     5SC70: 4 mm2: 2.1 x 2 (SC70 | 5)
5SOT-23: 5 mm2: 1.6 x 2.9 (SOT-23 | 5)    
SC70 | 5
SOT-23 | 5