This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC
The SN74LVC1G175 device has an asynchronous clear (CLR) input.
When CLR is high, data from the input pin (D) is transferred to the output
pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into
the low state, regardless of the clock edge or data on D.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using
Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.