SN74LVC2G08 デュアル 2入力 正論理 AND ゲート | TIJ.co.jp

SN74LVC2G08
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デュアル 2入力 正論理 AND ゲート

デュアル 2入力 正論理 AND ゲート - SN74LVC2G08
データシート
 

概要

This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G08 device performs the Boolean function A × B or Y = A\ + B\ in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For all available packages, see the orderable addendum at the end of the data sheet.

特長

  • Available in the Texas Instruments
    NanoStar™ and NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.7 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Can Be Used as a Down Translator to Translate
    Inputs From a Maximum of 5.5 V Down to the VCC
    Level
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

機能一覧

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Part number オーダー・オプション Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
SN74LVC2G08 ご注文 LVC     1.65     5.5     2     2     32     -32     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100     Catalog     -40 to 125
-40 to 85    
8DSBGA: 2 mm2: .98 x 1.98 (DSBGA | 8)
8DSBGA: 3 mm2: 2.25 x 1.25 (DSBGA | 8)
8SM8: 12 mm2: 4 x 2.95 (SM8 | 8)
8VSSOP: 6 mm2: 3.1 x 2 (VSSOP | 8)    
DSBGA | 8
DSBGA | 8
SM8 | 8
VSSOP | 8    
SN74LVC2G08-EP サンプルは利用できません。 LVC     1.65     5.5     2     2     32     -32     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100     HiRel Enhanced Product     -55 to 125     8VSSOP: 6 mm2: 3.1 x 2 (VSSOP | 8)     VSSOP | 8    
SN74LVC2G08-Q1 サンプルは利用できません。 LVC     1.65     5.5     2     2     32     -32     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100     Automotive     -40 to 85     8SM8: 12 mm2: 4 x 2.95 (SM8 | 8)     SM8 | 8