ProtocolsCAN, SBCNumber of channels (#)1Supply voltage(s) (V)5.5 to 30Bus fault voltage (V)-58 to 58Signaling rate (Max) (Mbps)8TI functional safety categoryFunctional Safety Quality-ManagedRatingAutomotiveOperating temperature range (C)-40 to 125Low power modeSleepCommon mode voltage (V)-12 to -12IsolatedNoHBM ESD (kV)-15 to 15open-in-newその他の CAN & LIN
The TCAN4550-Q1 is a CAN FD controller with an
integrated CAN FD transceiver supporting data rates up to 8 Mbps. The CAN FD controller meets the
specifications of the ISO11898-1:2015 high speed controller area network (CAN) data link layer and
meets the physical layer requirements of the ISO11898–2:2016 high speed CAN specification. The
TCAN4550-Q1 provides an interface between the CAN bus and the system processor
through serial peripheral interface (SPI), supporting both classic CAN and CAN FD, allowing port
expansion or CAN support with processors
that do not support CAN FD. The TCAN4550-Q1 provides CAN FD transceiver
functionality: differential transmit capability to the bus and differential receive capability from
the bus. The device supports wake up via local wake up (LWU) and bus
wake using the CAN bus implementing the ISO11898-2:2016 Wake Up Pattern (WUP).
The device includes many protection features providing device and CAN bus robustness.
These features include failsafe mode, internal dominant state timeout, wide bus operating range and a time-out watchdog as examples.
The SPI to CAN FD SBC + LIN BoosterPack™ plug-in module features the TCAN4550-Q1 CAN FD controller with integrated transceiver providing microcontrollers without an integrated CAN FD controller, or those needing additional channels, access to CAN FD applications through a SPI interface (...)
TCAN4550-Q1 CAN FD controller with integrated transceiver and SPI interface
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Common DB9 connector for supply voltage, CAN FD, and LIN bus signals
The EVM can be used to evaluate the TCAN4550 SPI to CAN FD Controller and Transceiver solution. The CAN bus signals are easily accessed via a DB9 connector (or via header pins), and the digital interface (SPI lines plus GPIOs) is accessible via a single dual-row header. Input clocks to (...)
Provides access to CAN bus, SPI, clock, and all GPIO signals
Clock input can be configured for on-board crystal or external clock source
CAN bus termination can be enabled/disabled via jumpers
Status LEDs indicate board power status and GPIO pin states