TLV314 TLVx314 3MHz、低消費電力、低ノイズ、RRIO CMOS オペ・アンプ | TIJ.co.jp

TLV314
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TLVx314 3MHz、低消費電力、低ノイズ、RRIO CMOS オペ・アンプ

 

概要

The TLV314 family of single-, dual-, and quad-channel operational amplifiers represents a new generation of low-power, general-purpose operational amplifiers. Rail-to-rail input and output swings (RRIO), low quiescent current (150 µA typically at 5 V) combine with a wide bandwidth of 3 MHz to make this family very attractive for a variety of battery-powered applications that require a good balance between cost and performance. Additionally, the TLV314 family architecture achieves a low input bias current of 1 pA, allowing for applications with MΩ source impedances.

The robust design of the TLV314 devices provides ease-of-use to the circuit designer: unity-gain stability, RRIO, capacitive loads of up to 300 pF, an integrated RF/EMI rejection filter, no phase reversal in overdrive conditions, and high electrostatic discharge (ESD) protection (4-kV HBM).

These devices are optimized for low-voltage operation as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V), and are specified over the extended industrial temperature range of –40°C to +125°C.

The TLV314 (single) is available in both 5-pin SC70 and SOT-23 packages. The TLV2314 (dual) is offered in 8-pin SOIC and VSSOP packages. The quad-channel TLV4314 is offered in a 14-pin TSSOP package.

特長

  • Low Offset Voltage: 0.75 mV (typ)
  • Low Input Bias Current: 1 pA (typ)
  • Wide Supply Range: 1.8 V to 5.5 V
  • Rail-to-Rail Input and Output
  • Gain Bandwidth: 3 MHz
  • Low IQ: 250 µA/Ch (max)
  • Low Noise: 16 nV/√Hz at 1 kHz
  • Internal RF/EMI Filter
  • Extended Temperature Range:
    –40°C to +125°C

機能一覧

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Part number オーダー・オプション Number of channels (#) Total supply voltage (Min) (+5V=5, +/-5V=10) Total supply voltage (Max) (+5V=5, +/-5V=10) GBW (Typ) (MHz) Slew rate (Typ) (V/us) Rail-to-rail Vos (offset voltage @ 25 C) (Max) (mV) Iq per channel (Typ) (mA) Vn at 1 kHz (Typ) (nV/rtHz) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG) Offset drift (Typ) (uV/C) Features Input bias current (Max) (pA) CMRR (Typ) (dB) Output current (Typ) (mA) Architecture
TLV314 ご注文 1     1.8     5.5     3     1.5     In
Out    
3     0.15     16     Catalog     -40 to 125     SC70 | 5
SOT-23 | 5    
5SC70: 4 mm2: 2.1 x 2 (SC70 | 5)
5SOT-23: 5 mm2: 1.6 x 2.9 (SOT-23 | 5)    
2     Cost Optimized
EMI Hardened    
  96     20     CMOS    
OPA314 ご注文 1     1.8     5.5     3     1.5     In
Out    
2.5     0.15     14     Catalog     -40 to 125     SC70 | 5
SOT-23 | 5    
5SC70: 4 mm2: 2.1 x 2 (SC70 | 5)
5SOT-23: 5 mm2: 1.6 x 2.9 (SOT-23 | 5)    
1     EMI Hardened     10     80     20     CMOS    
TLV2314 ご注文 2     1.8     5.5     3     1.5     In
Out    
3     0.15     16     Catalog     -40 to 125     SOIC | 8
VSSOP | 8    
8SOIC: 19 mm2: 3.91 x 4.9 (SOIC | 8)
8VSSOP: 15 mm2: 4.9 x 3 (VSSOP | 8)    
2     Cost Optimized
EMI Hardened    
  96     20     CMOS    
TLV2771 ご注文 1     2.5     5.5     5.1     10.5     In to V-
Out    
2.5     1     17     Catalog     -40 to 125
0 to 70    
SOIC | 8
SOT-23 | 5    
8SOIC: 19 mm2: 3.91 x 4.9 (SOIC | 8)
5SOT-23: 5 mm2: 1.6 x 2.9 (SOT-23 | 5)    
2         60     96     40     CMOS    
TLV4314 ご注文 4