製品の詳細

DSP 1 C55x DSP MHz (Max) 100, 120 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (C) -40 to 85
DSP 1 C55x DSP MHz (Max) 100, 120 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (C) -40 to 85
NFBGA (ZCH) 196 100 mm² 10 x 10
  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core.

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core.

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

ダウンロード

Limited design support from TI available

This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.

技術資料

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41 資料すべて表示
種類 タイトル 英語版のダウンロード 日付
* データシート TMS320C5515 Fixed-Point Digital Signal Processor データシート (Rev. F) 2013年 10月 21日
* エラッタ TMS320C5515/C5514 Fixed-Point DSP Silicon Errata (Silicon Revision 2.0) (Rev. D) 2015年 7月 15日
アプリケーション・ノート How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) 2021年 5月 19日
アプリケーション・ノート Using the TMS320C5515/14/05/04 Bootloader (Rev. D) 2019年 11月 25日
アプリケーション・ノート TMS320C5505/15/35 Schematic Checklist 2019年 2月 14日
技術記事 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
技術記事 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
アプリケーション・ノート MEMS Microphone Direct PDM Input via I2S to a C5515 EVM With Software Decimation 2016年 9月 22日
アプリケーション・ノート Usage Guidelines for C55x On-Chip Low Dropout Regulators (LDOs) 2016年 7月 26日
技術記事 Clove: Low-Power video solutions based on Sitara™ AM57x processors 2016年 7月 21日
アプリケーション・ノート Power Estimation and Pwr Consumption Sum for TMS320C5504/05/14/15/32/33/34/35 (Rev. A) 2016年 4月 4日
アプリケーション・ノート Instructions to Benchmark C55 DSP Library 2016年 4月 1日
技術記事 TI's new DSP Benchmark Site 2016年 2月 8日
アプリケーション・ノート C5000 DSP-Based Low-Power System Design 2015年 11月 30日
ユーザー・ガイド TMS320C5515/14/05/04/VC05/VC04 DSP MMC/SD Card Controller User's Guide (Rev. B) 2015年 9月 30日
アプリケーション・ノート Migrating from TMS320C5515 to 5525 2014年 4月 2日
ユーザー・ガイド TMS320C5515/14/05/04 DSP Universal Serial Bus 2.0 (USB) Controller User's Guide (Rev. A) 2013年 10月 3日
アプリケーション・ノート FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs (Rev. B) 2013年 1月 9日
ユーザー・ガイド TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User's Guide (Rev. B) 2012年 11月 18日
ユーザー・ガイド TMS320C5515/14/05/04 DSP Real-Time Clock (RTC) User's Guide (Rev. A) 2012年 11月 15日
ユーザー・ガイド TMS320C5515 DSP System User's Guide (Rev. E) 2012年 9月 14日
ユーザー・ガイド TMS320C5515/14/05/04 DSP Inter-IC Sound (I2S) Bus User's Guide (Rev. B) 2012年 8月 9日
ユーザー・ガイド TMS320C5515/14/05/04 DSP Direct Memory Access (DMA) Controller User's Guide (Rev. A) 2012年 3月 7日
ユーザー・ガイド TMS320C5515/05/VC05 DSP Successive Approx. Register (SAR) ADC User's Guide (Rev. C) 2012年 1月 13日
アプリケーション・ノート Migrating from TMS320C5515/05 to TMS320C5535/34/33/32 (Rev. A) 2011年 12月 22日
ユーザー・ガイド TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 2011年 12月 15日
ユーザー・ガイド TMS320C55x Assembly Language Tools User's Guide (Rev. I) 2011年 11月 9日
ユーザー・ガイド TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. G) 2011年 11月 9日
その他の技術資料 C5515 eZdsp (Rev. A) 2010年 11月 8日
その他の技術資料 TMS320C5514 and TMS320C5515 DSP Product Bulletin 2010年 1月 18日
その他の技術資料 C5504/05 Product Bulletin 2010年 1月 12日
その他の技術資料 Low-power signal chain solutions based on C5515 DSP for portable medical applica 2010年 1月 12日
ユーザー・ガイド Corazo'n Line22 2009年 9月 21日
ユーザー・ガイド Corazo'n Line23 2009年 9月 21日
ユーザー・ガイド Corazo'n Line24 2009年 9月 21日
ユーザー・ガイド Corazo'n Line25 2009年 9月 21日
ユーザー・ガイド Corazo'n Line33 2009年 9月 21日
ユーザー・ガイド TMS320VC5505 DSP Inter-Integrated Circuit Peripheral User's Guide (Rev. A) 2009年 9月 21日
ユーザー・ガイド TMS320C55x 3.0 DSP Algebraic Instruction Set Reference Guide (Rev. E) 2009年 6月 24日
ユーザー・ガイド TMS320C55x 3.0 DSP Mnemonic Instruction Set Reference Guide (Rev. E) 2009年 6月 24日
ユーザー・ガイド TMS320C55x DSP CPU Reference Guide, Version 3.0 (Rev. E) 2009年 6月 17日

設計と開発

追加の事項や他のリソースを参照するには、以下のタイトルをクリックすると、詳細ページを表示できます。

評価ボード

TMDX5515EZDSP — C5515 eZDSP USB スティック開発ツール

The TMDX5515eZDSP is a small form factor, very low cost USB-powered DSP development tool which includes all the hardware and software needed to evaluate the industry’s lowest power 16-bit DSP : TMS320C5515. This tool is similar to TMDX5505eZdsp in the form factor but provides more evaluation (...)

在庫あり
制限: 1
デバッグ・プローブ

TMDSEMU200-U — Spectrum Digital XDS200 USB エミュレータ

Spectrum Digital XDS200 は、TI のプロセッサを対象とする最新の XDS200 デバッグ・プローブ(エミュレータ)ファミリの最初のモデルです。XDS200 ファミリは、超低コストの XDS100 と高性能の XDS560v2 の間で、低コストと高性能の最適バランスを実現します。また、すべての XDS デバッグ・プローブは、ETB(Embedded Trace Buffer、組込みトレース・バッファ)を搭載したすべての ARM と DSP プロセッサに対し、コア・トレースとシステム・トレースをサポートしています。

Spectrum Digital XDS200 は、TI (...)

在庫あり
制限: 3
デバッグ・プローブ

TMDSEMU560V2STM-U — Blackhawk XDS560v2 システム・トレース USB エミュレータ

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

在庫あり
制限: 1
デバッグ・プローブ

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

在庫あり
制限: 1
アプリケーション・ソフトウェアとフレームワーク

C55X-AUDIOFRAMEWORK — C55x 接続オーディオ・フレームワーク

The TMS320C55x™ Connected Audio Framework provides a software framework which allows the C55x devices to operate as a USB Audio peripheral. In addition to providing this capability, the framework can be extended by users by the incorporation of audio processing algorithms in the record and (...)
ドライバまたはライブラリ

SPRC100 — TMS320C55x DSP ライブラリ

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
ドライバまたはライブラリ

SPRC133 — TMS320C55x チップ・サポート・ライブラリ

C55x チップ・サポート・ライブラリ(CSL)は、DSP オンチップ・ペリフェラル構成/制御用の使いやすいアプリケーション・プログラミング・インターフェイス(API)です。ハードウェアが抽象化され、各種 C55x デバイス間の互換性が確保されています。CSL は開発環境の標準化と移植性を実現し、開発期間の短縮を可能にします。
  • C55x CSL(SPRC133): この機能セクションに掲載されている機能は、C5501、C5502、C5509、C5509A、C5510、C5510A を含む TMS320C55x DSP 向けに設計されたものです。
  • C55x CSL - Low Power (...)
ドライバまたはライブラリ

SPRC264 — C64x+IMGLIB

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
ドライバまたはライブラリ

TELECOMLIB — テレコムおよびメディア向けライブラリ - FAXLIB、VoLIB および AEC/AER、TMS320C64x+ および TMS320C55x プロセッサ用

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
ソフトウェア・コーデック

C55XCODECS — コーデック - C55x デバイス向けに最適化

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
ソフトウェア・コーデック

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies 社の DSP VOIP、スピーチ / オーディオ・コーデック

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
Adaptive Digital Technologies, Inc. からの提供
ソフトウェア・コーデック

ALGOT-3P-DSPVOIPCODECS — Algotron 社の C5000 DSP 向け テレコムとオーディオ・コーデック

Algotron provides C5000 DSP software modules for telecoms & audio. Examples are: modem data pumps, speech coders, signal generators & detectors for DTMF and caller ID. All modules feature simple yet flexible interfaces with full re-entrancy. They come with user's guides, example (...)
Algotron からの提供
ソフトウェア・コーデック

COUTH-3P-DSPVOIPCODECS — CouthIT DSP VoIP、スピーチ、オーディオ・コーデック

Since 1999, CouthIT has been helping customers transform their ideas into real-time robust software solutions. They license specialized, pre-built, highly optimized software modules in the areas of VoIP and speech and audio codecs, and provide software optimization and customization services for (...)
Couth Infotech Pvt. Ltd. からの提供
ソフトウェア・コーデック

DSPI-3P-DSPVOIPCODECS — DSP Innovations 社の DSP VoIP コーデック

DSP Innovations is a supplier of C5000TM DSP-software and engineering services. Proprietary and standard vocoders from DSPINI have superior characteristics, operate in range from 300 bps up to 64 kbps and are used in: secure voice, software defined radio, wireless, VoIP, voice storage, and more. (...)
DSP Innovations からの提供
ソフトウェア・コーデック

SCORP-3P-DSPAUDIOCODECS — Spirit 社の DSP オーディオとスピーチ・コーデック

Since inception in 1992 SPIRIT has become a global brand in top quality voice, audio and data communication software products and is well known for innovation. SPIRIT is a technology enabling company, leveraging its extensive experience in smart carrier-grade solutions for voice and video (...)
Spirit DSP からの提供
ソフトウェア・コーデック

VOCAL-3P-DSPVOIPCODECS — Vocal Technologies の DSP VoIP コーデック

25 年を超えるアセンブリおよび C コード開発の実績がある Vocal のモジュール式ソフトウェア・スイートは、さまざまな TI DSP で利用できます。対象とする製品には、ATA、VoIP サーバーおよびゲートウェイ、HPNA ベースの IPBX、ビデオ監視、音声およびビデオ会議、音声およびデータ RF デバイス、RoIP ゲートウェイ、政府機関向けセキュア・デバイス、合法的傍受ソフトウェア、医療用デバイス、組み込みモデム、T.38 ファックス、FoIP などがあります。

Vocal Technologies の詳細については https://www.vocal.com をご覧ください。
VOCAL Technologies, Ltd. からの提供
シミュレーション・モデル

C5515 ZCH BSDL Model

SPRM496.ZIP (5 KB) - BSDL Model
シミュレーション・モデル

C5515 ZCH IBIS Model

SPRM497.ZIP (445 KB) - IBIS Model
設計ツール

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
パッケージ ピン数 ダウンロード
NFBGA (ZCH) 196 オプションの表示

購入と品質

含まれる情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL rating/ リフローピーク温度
  • MTBF/FIT の推定値
  • 原材料組成
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果

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