Communications infrastructure digital signal processor
製品の詳細
パラメータ
特長
- High-Performance Fixed-Point DSP (C6457)
- 1.18-ns, 1-ns, and 0.83-ns Instruction Cycle Time/li>
- 850-MHz, 1-GHz, and 1.2-GHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 8000 and 9600 MIPS/MMACS (16-Bits)
- Case Temperature
- Commercial:
- 0°C to 100°C (850 MHz)
- 0°C to 100°C (1 GHz)
- 0°C to 95°C (1.2 GHz)
- Extended:
- -40°C to 100°C (1 GHz)
- -40°C to 95°C (1.2 GHz)
- Commercial:
- TMS320C64x+™ DSP Core
- Dedicated SPLOOP Instruction
- Compact Instructions (16-Bit)
- Instruction Set Enhancements
- Exception Handling
- TMS320C64x+ Megamodule L1/L2 Memory Architecture:
- 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped]
- 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative]
- 16M-Bit (2048K-Byte) L2 Unified Mapped Ram/Cache [Flexible Allocation]
- Configurable up to 1MB of L2 Cache
- 512K-Bit (64K-Byte) L3 ROM
- Time Stamp Counter
- Enhanced VCP2
- Supports Over 694 7.95-Kbps AMR
- Programmable Code Parameters
- Two Enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)
- Each TCP2 Supports up to Eight 2-Mbps 3GPP (6 Iterations)
- Programmable Turbo Code and Decoding Parameters
- Endianess: Little Endian, Big Endian
- 64-Bit External Memory Interface (EMIFA)
- Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM)
- Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
- 32M-Byte Total Addressable External Memory Space
- 32-Bit DDR2 Memory Controller (DDR2-667 SDRAM)
- Four 1× Serial RapidIO® Links (or One 4×), v1.3 Compliant
- 1.25-, 2.5-, 3.125-Gbps Link Rates
- Message Passing, DirectIO Support, Error Mgmt Extensions, Congestion Control
- IEEE 1149.6 Compliant I/Os
- EDMA3 Controller (64 Independent Channels)
- 32-/16-Bit Host-Port Interface (HPI)
- Two 1.8-V McBSPs
- 10/100/1000 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Supports SGMII, v1.8 Compliant
- 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
- Two 64-Bit General-Purpose Timers
- Configurable as Four 32-Bit Timers
- Configurable in a Watchdog Timer Mode
- UTOPIA
- UTOPIA Level 2 Slave ATM Controller
- 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
- User-Defined Cell Format up to 64 Bytes
- One 1.8-V Inter-Integrated Circuit (I2C) Bus
- 16 General-Purpose I/O (GPIO) Pins
- System PLL and PLL Controller
- DDR PLL, Dedicated to DDR2 Memory Controller
- Advanced Event Triggering (AET) Compatible
- Trace-Enabled Device
- Supports IP Security
- IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
- 688-Pin Ball Grid Array (BGA) Package (CMH or GMH Suffix), 0.8-mm Ball Pitch
- 0.065-µm/7-Level Cu Metal Process (CMOS)
- 3.3-V, 1.8-V, 1.1-V I/Os, 1.1-V and 1.2-V Internal
All trademarks are the property of their respective owners.
概要
The TMS320C64x+™ DSPs (including the TMS320C6457 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6457 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.
Based on 65-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6457 device offers cost-effective solutions to high-performance DSP programming challenges. The C6457 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit × 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit × 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit × 32-bit MAC or four 8-bit × 8-bit MACs every clock cycle.
The C6457 device includes Serial RapidIO®. This high-bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.
The C6457 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the C6457 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache whereas L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. L2 is configurable up to 1MB of cache. The C64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient interface between the C6457 DSP core processor and the network; a management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA), which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.
The C6457 device has three high-performance embedded coprocessors [one enhanced Viterbi Decoder Coprocessor (VCP2) and two enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)] that significantly speed up channel-decoding operations on-chip. The VCP2 operating at CPU clock ÷ 3 can decode more than 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Each TCP2 operating at CPU clock ÷ 3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP2/TCP2s and the CPU are carried out through the EDMA3 controller.
The C6457 device has a complete set of development tools, which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.
No design support from TI available
This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.
技術資料
設計と開発
追加の事項や他のリソースを参照するには、以下のタイトルをクリックすると、詳細ページを表示できます。ハードウェア開発
概要
eInfochips は、製品エンジニアリングおよび設計サービスの企業です。20 年以上の経験、500 を超える製品開発、世界 140 か国でのサービス実績は 4000 万回を超えています。複数の業界にまたがる多くの Fortune 500企業にターンキー・テクノロジー・ソリューションを提供しています。アロー・カンパニーである eInfochips は、プロトタイプの製造から生産まで、さらに認定までも支援できる製造パートナーのための強力なエコシステムを提供します。生産の移行に伴う変更を低減するために、委託製造業者と緊密に連携して、テスト(DFT)と製造(DFM)に対して設計を最適化します。eInfochips のシステム・オン・モジュール(SOM)と価モジュール(EVM)は、テキサス・インスツルメンツのデジタル信号プロセッサ(DSP)およびメディア・プロセッサ向けに設計されています。
概要
Spectrum Digital XDS200 は、TI のプロセッサを対象とする最新の XDS200 デバッグ・プローブ(エミュレータ)ファミリの最初のモデルです。XDS200 ファミリは、超低コストの XDS100 と高性能の XDS560v2 の間で、低コストと高性能の最適バランスを実現します。また、すべての XDS デバッグ・プローブは、ETB(Embedded Trace Buffer、組込みトレース・バッファ)を搭載したすべての ARM と DSP プロセッサに対し、コア・トレースとシステム・トレースをサポートしています。
Spectrum Digital XDS200 は、TI 20 ピン・コネクタ(TI 14 ピン、ARM 10 ピン、ARM 20 ピンを接続するための複数のアダプタ付属)とホスト側の USB 2.0 (...)
特長
XDS200 は、TI のプロセッサを対象とする最新の JTAG デバッグ・プローブ(エミュレータ)ファミリです。高い性能と一般的な機能を搭載した低コスト XDS100 と高性能 XDS560v2 の中間に位置する XDS200 は、TI のマイコン、プロセッサ、ワイヤレス・デバイスのデバッグのためのバランス重視のソリューションを提供します。
XDS200 は、販売開始から長い年月が経過している「XDS510」JTAG デバッガ・ファミリに比べ、データ・スループットが高いほか、ARM シリアル・ワイヤ・デバッグ・モードのサポート機能も追加しており、コスト低減を可能にします。
TI では開発ボードのスペース低減を推進しており、すべての XDS200 派生製品は、ターゲット接続用のプライマリ JTAG コネクティビティとして標準的な TI 20 ピン・コネクタを実装しています。この製品に加えて、すべての派生製品は、TI と ARM の標準的な JTAG ヘッダーに接続するためにモジュラー形式のターゲット構成アダプタも採用しています(付属するアダプタは、モデルによって異なります)。
XDS200 は、従来型の IEEE1149.1(JTAG)、IEEE1149.7(cJTAG)、ARM のシリアル・ワイヤ・デバッグ(SWD)とシリアル・ワイヤ出力(SWO)をサポートしており、+1.5V ~ 4.1V のインターフェイス・レベルで動作します。
IEEE1149.7 つまり Compact JTAG(cJTAG)は、従来型の JTAG を大幅に改良しており、2 本のピンだけで従来型のすべての機能をサポートします。また、TI のワイヤレス・コネクティビティ・マイコンでの利用も可能です。
シリアル・ワイヤ・デバッグ(SWD)とは、同じく 2 本のピンを使用して、JTAG より高速なクロック・レートでデータを転送するデバッグ・モードです。シリアル・ワイヤ出力(SWO)を使用する場合は、もう 1 本のピンを追加して、Cortex M4 マイコンで簡潔なトレース動作を実行することができます。
すべての XDS200 モデルは、ホストへの接続のために、USB2.0 ハイスピード(480Mbps)をサポートしており、一部のモデルではイーサネット 10/100Mbps もサポートしています。また、一部のモデルではターゲット・ボードでの消費電力監視をサポートしています。
XDS200 ファミリには、TI の (...)
概要
The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The (...)
特長
XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)
概要
The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The (...)
特長
-
XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)
ソフトウェア開発
NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.
Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices (...)
特長
MCSDK
Provides foundational software for ARM+DSP devices. It encapsulates a collection of software elements and tools intended to enable customer application development.
The foundational components include:
- SYS/BIOS real-time embedded operating system on DSP cores
- Linux high-level operating system (...)
特長
The STK-MED contains optimized C64x+ DSP software for processing blocks commonly found in a medical imaging system. The STK-MED contains a detailed algorithm description, API documentation, benchmarks and test bench for each software module.
The software and test benches can either be run on a CCS (...)
また、このリリースは、FastRTS ライブラリで使用できる一部の関数に対応する C の実装も収録しています。これらの C コードを使用すると、ユーザーの皆様はこれらの関数をインライン化し、さらに性能を改善できます。
特長
単精度と倍精度の算術関数 | 単精度と倍精度の変換関数 |
浮動小数点の加算 | 浮動小数点から 32 ビット符号付き整数への変換 |
32 ビット符号付き整数から浮動小数点への変換 | |
浮動小数点の除算 | 浮動小数点から 40 ビット符号付き長整数への変換 |
40 ビット符号付き長整数から浮動小数点への変換 | |
浮動小数点の乗算 | 浮動小数点から 32 ビット符号なし整数への変換 |
32 ビット符号なし整数から浮動小数点への変換 | |
浮動小数点の逆数 | 浮動小数点から 40 ビット符号なし長整数への変換 |
40 ビット符号なし長整数から浮動小数点への変換 | |
浮動小数点の減算 | 倍精度浮動小数点から単精度浮動小数点への変換 |
単精度浮動小数点から倍精度浮動小数点への変換 |
特長
Image Analysis
- Image boundry and perimeter
- Morphological operation
- Edge detection
- Image Histogram
- Image thresholding
Image filtering and format conversion
- Color space conversion
- Image convolution
- Image correlation
- Error diffusion
- Median filtering
- Pixel expansion
Image compression and decompression
- Forward and (...)
特長
Optimized DSP routines including functions for:
- Adaptive filtering
- Correlation
- FFT
- Filtering and convolution: FIR, biquad, IIR, convolution
- Math: Dot products, max value, min value, etc.
- Matrix operations
特長
For best design results, find the codec(s) optimized for your platform. If none are available, click GET SOFTWARE button (above) for codecs optimized for TI C64x+ core-based devices (i.e. most devices in the OMAP35x, TMS320C645x, TMS320C647x, TMS320DM646x, TMS320DM644x and TMS320DM643x families).
- For (...)
Vocal Technologies の詳細については https://www.vocal.com をご覧ください。
設計ツールとシミュレーション
特長
- Supports many TI processors including Sitara and Jacinto Processors and DSPs
- Search by type of product, TI devices supported, or country
- Links and contacts for quick engagement
- Third-party companies located around the world
CAD/CAE シンボル
パッケージ | ピン数 | ダウンロード |
---|---|---|
(CMH) | 688 | オプションの表示 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL rating/ リフローピーク温度
- MTBF/FIT の推定値
- 原材料組成
- 認定試験結果
- 継続的な信頼性モニタ試験結果