TMS320C6743

BGA (ZKB)

256

289 mm² 17 x 17

HLQFP (PTP)

176

—

Applications
- Networking
- High-Speed Encoding
- Professional Audio™
Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- 3000 MIPS and 2250 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 128KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
3.3-V LVCMOS I/Os
Two External Memory Interfaces:
- EMIFA
  - NOR (8-Bit-Wide Data)
  - NAND (8-Bit-Wide Data)
- EMIFB
  - 16-bit SDRAM, up to 128MB
Two Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
One Serial Peripheral Interface (SPI) with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled Through Software to Save Power
  - Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
Two Multichannel Audio Serial Ports (McASPs):
- Supports TDM, I2S, and Similar Formats
- FIFO Buffers for Transmit and Receive
10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Event Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
Commercial or Automotive Temperature

Applications
- Networking
- High-Speed Encoding
- Professional Audio™
Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- 3000 MIPS and 2250 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 128KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
3.3-V LVCMOS I/Os
Two External Memory Interfaces:
- EMIFA
  - NOR (8-Bit-Wide Data)
  - NAND (8-Bit-Wide Data)
- EMIFB
  - 16-bit SDRAM, up to 128MB
Two Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
One Serial Peripheral Interface (SPI) with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled Through Software to Save Power
  - Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
Two Multichannel Audio Serial Ports (McASPs):
- Supports TDM, I2S, and Similar Formats
- FIFO Buffers for Transmit and Receive
10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Event Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
Commercial or Automotive Temperature

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.

The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I²C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.

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技術資料

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39 資料すべて表示

	種類	タイトル	日付
*	データシート	TMS320C6743 Fixed- and Floating-Point Digital Signal Processor データシート (Rev. D)	2014年 6月 17日
*	エラッタ	TMS320C6743 Fixed/Floating-Point DSP SE (Silicon Revs 3.0, 2.1, 2.0, 1.1, & 1.0) (Rev. G)	2014年 6月 17日
*	ユーザー・ガイド	TMS320C6743 DSP Technical Reference Manual (Rev. D)	2016年 9月 21日
	アプリケーション・ノート	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	2021年 5月 19日
	ユーザー・ガイド	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)	2020年 6月 1日
	アプリケーション・ノート	FFT	2019年 6月 11日
	アプリケーション・ノート	Programming PLL controllers on OMAP-L1x8/C674x/AM18xx	2019年 4月 25日
	アプリケーション・ノート	TMS320C6747/45/43 Power Consumption Summary	2019年 4月 23日
	アプリケーション・ノート	General Hardware Design/BGA PCB Design/BGA Decoupling	2019年 2月 22日
	アプリケーション・ノート	Digital Audio With McASP	2019年 1月 10日
	技術記事	Bringing the next evolution of machine learning to the edge	2018年 11月 27日
	技術記事	How quality assurance on the Processor SDK can improve software scalability	2018年 8月 22日
	ユーザー・ガイド	OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D)	2016年 9月 21日
	技術記事	Clove: Low-Power video solutions based on Sitara™ AM57x processors	2016年 7月 21日
	技術記事	TI's new DSP Benchmark Site	2016年 2月 8日
	アプリケーション・ノート	Plastic Ball Grid Array [PBGA] Application Note (Rev. B)	2015年 8月 13日
	ユーザー・ガイド	System Analyzer User's Guide (Rev. F)	2013年 11月 18日
	ユーザー・ガイド	TMS320C6000 Assembly Language Tools v 7.3 User's Guide (Rev. W)	2012年 8月 21日
	ユーザー・ガイド	TMS320C6000 Optimizing Compiler v 7.3 User's Guide (Rev. U)	2012年 8月 21日
	アプリケーション・ノート	Using the OMAP-L1x7 Bootloader (Rev. G)	2012年 6月 1日
	アプリケーション・ノート	Using the TMS320C6747/45/43 Bootloader (Rev. C)	2012年 6月 1日
	アプリケーション・ノート	Power Consumption Guide for the C66x	2011年 10月 6日
	ユーザー・ガイド	TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F)	2011年 9月 14日
	ホワイト・ペーパー	Middleware/Firmware design challenges due to dynamic raw NAND market	2011年 5月 19日
	ユーザー・ガイド	TMS320C674x DSP Megamodule Reference Guide (Rev. A)	2010年 8月 3日
	ユーザー・ガイド	TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B)	2010年 7月 30日
	ユーザー・ガイド	TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S)	2010年 3月 18日
	ユーザー・ガイド	TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q)	2010年 3月 18日
	アプリケーション・ノート	OMAP-L137 TMS320C6747/C6745/C6743 Pin Multiplexing Utility (Rev. A)	2009年 9月 26日
	アプリケーション・ノート	TMS320C6747/45/43 Complementary Products	2009年 9月 23日
	ホワイト・ペーパー	Efficient fixed- and floating-point code execution on the TMS320C674x core	2009年 6月 24日
	アプリケーション・ノート	TMS320DM674x/OMAP-L1x Universal Bus Downstream Compliance Testing	2009年 3月 12日
	アプリケーション・ノート	TMS320DM674x/OMAP-L1x Universal Serial Bus Upstream Device Compliance Testing	2009年 3月 12日
	アプリケーション・ノート	TMS320DM67x/OMAP-L1x USB Compliance Checklist	2009年 3月 12日
	ユーザー・ガイド	TMS320C674x DSP Cache User's Guide (Rev. A)	2009年 2月 11日
	ユーザー・ガイド	TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q)	2008年 5月 15日
	ユーザー・ガイド	TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O)	2008年 5月 15日
	ユーザー・ガイド	TMS320C6000 Assembly Language Tools v 6.0 Beta User's Guide (Rev. P)	2006年 10月 31日
	ユーザー・ガイド	TMS320C6000 Optimizing Compiler v 6.0 Beta User's Guide (Rev. N)	2005年 7月 29日

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