TMS320VC5441 は新規設計での使用を推奨しません
従来の設計をサポートできるようにこの製品は引き続き生産中ですが、TI はこの製品を新規の設計には推奨しません。以下の代替品のいずれかをご検討ください。
open-in-new 代替品と比較
比較対象デバイスと類似の機能
TMS320C6657 アクティブ 高性能デュアル・コア C66x 固定小数点 / 浮動小数点 DSP - 最大 1.25GHz、2 個の UART 搭載 This product is a newer generation of floating point DSPs with higher performance & improved connectivity options.

製品詳細

DSP type 4 C54x DSP (max) (MHz) 133 Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 4 C54x DSP (max) (MHz) 133 Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 0
LQFP (PGF) 176 676 mm² 26 x 26
  • 532-MIPS Quad-Core DSP Consisting of Four Independent Subsystems
  • Each Core has an Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core
  • Each Core has a 17-Bit × 17-Bit Parallel Multiplier Coupled to a 40-Bit Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operations
  • Each Core has a Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Each Core has an Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Each Core has Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Total 640K-Word × 16-Bit Dual-Access On-Chip RAM (256K-Word x 16-Bit Shared Memory and 96K-Word x 16-Bit Local Memory Per Subsystem)
  • Single-Instruction Repeat and Block-Repeat Operations
  • Instructions With 32-Bit Long Word Operands
  • Instructions With 2 or 3 Operand Reads
  • Fast Return From Interrupts
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Output Control of CLKOUT
  • Output Control of Timer Output (TOUT)
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions
  • Dual 1.6-V (Core) and 3.3-V (I/O) Power Supplies for Low-Power, Fast Operations
  • 7.5-ns Single-Cycle Fixed-Point Instruction
  • Twenty-Four Channels of Direct Memory Access (DMA) for Data Transfers With No CPU Loading (Six Channels Per Subsystem)
  • Twelve Multichannel Buffered Serial Ports (McBSPs), Each With 128-Channel Selection Capability (Three McBSPs per Subsystem)
  • 16-Bit Host-Port Interface (HPI)
  • Software-Programmable Phase-Locked Loop (PLL) Provides Several Clocking Options (Requires External TTL Oscillator)
  • On-Chip Scan-Based Emulation Logic, IEEE Standard 1149.1 (JTAG) Boundary-Scan Logic
  • Four Software-Programmable Timers (One Per Subsystem)
  • Four Software-Programmable Watchdog Timers (One Per Subsystem)
  • Sixteen General-Purpose I/Os (Four Per Subsystem)
  • Provided in 176-pin Plastic Low-Profile Quad Flatpack (LQFP) Package (PGF Suffix)
  • Provided in 169-ball MicroStar BGA™ Package (GGU Suffix)

MicroStar BGA is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990, Standard Test-Access Port and Boundary Scan Architecture.
NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).
NOTE: Leading "x" in signal names identifies the subsystem; x = A, B, C, or D for subsystem A, B, C, or D, respectively. Trailing "n" in signal names identifies the McBSP; n = 0, 1, or 2 for McBSP0, McBSP1, or McBSP2, respectively.

  • 532-MIPS Quad-Core DSP Consisting of Four Independent Subsystems
  • Each Core has an Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core
  • Each Core has a 17-Bit × 17-Bit Parallel Multiplier Coupled to a 40-Bit Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operations
  • Each Core has a Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Each Core has an Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Each Core has Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Total 640K-Word × 16-Bit Dual-Access On-Chip RAM (256K-Word x 16-Bit Shared Memory and 96K-Word x 16-Bit Local Memory Per Subsystem)
  • Single-Instruction Repeat and Block-Repeat Operations
  • Instructions With 32-Bit Long Word Operands
  • Instructions With 2 or 3 Operand Reads
  • Fast Return From Interrupts
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Output Control of CLKOUT
  • Output Control of Timer Output (TOUT)
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions
  • Dual 1.6-V (Core) and 3.3-V (I/O) Power Supplies for Low-Power, Fast Operations
  • 7.5-ns Single-Cycle Fixed-Point Instruction
  • Twenty-Four Channels of Direct Memory Access (DMA) for Data Transfers With No CPU Loading (Six Channels Per Subsystem)
  • Twelve Multichannel Buffered Serial Ports (McBSPs), Each With 128-Channel Selection Capability (Three McBSPs per Subsystem)
  • 16-Bit Host-Port Interface (HPI)
  • Software-Programmable Phase-Locked Loop (PLL) Provides Several Clocking Options (Requires External TTL Oscillator)
  • On-Chip Scan-Based Emulation Logic, IEEE Standard 1149.1 (JTAG) Boundary-Scan Logic
  • Four Software-Programmable Timers (One Per Subsystem)
  • Four Software-Programmable Watchdog Timers (One Per Subsystem)
  • Sixteen General-Purpose I/Os (Four Per Subsystem)
  • Provided in 176-pin Plastic Low-Profile Quad Flatpack (LQFP) Package (PGF Suffix)
  • Provided in 169-ball MicroStar BGA™ Package (GGU Suffix)

MicroStar BGA is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990, Standard Test-Access Port and Boundary Scan Architecture.
NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).
NOTE: Leading "x" in signal names identifies the subsystem; x = A, B, C, or D for subsystem A, B, C, or D, respectively. Trailing "n" in signal names identifies the McBSP; n = 0, 1, or 2 for McBSP0, McBSP1, or McBSP2, respectively.

The TMS320VC5441 fixed-point digital signal processor is a quad-core solution running at 532-MIPS performance. The 5441 consists of four DSP subsystems with shared program memory. Each subsystem consists of one TMS320C54x™ DSP core, 32K-word program/data DARAM, 64K-word data DARAM, three multichannel buffered serial ports, DMA logic, one watchdog timer, one general-purpose timer, and other miscellaneous circuitry.

The 5441 also contains a host-port interface (HPI) that allows the 5441 to be viewed as a memory-mapped peripheral to a host processor.

Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5441 includes the control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the 5441 has a total of 256K words of shared program memory (128K words shared by subsystems A and B, and another 128K words shared by subsystems C and D).

The 5441 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over IP subsystems. It is designed to maintain the current modem architecture with minimal hardware and software impacts, thus maximizing reuse of existing modem technologies and development efforts.

The 5441 is offered in two temperature ranges and individual part numbers are shown below. (Please note that the industrial temperature device part numbers do not follow the typical numbering tradition.)

Commercial temperature devices (0°C to 85°C)
       TMS320VC5441PGF532 (176-pin LQFP)
       TMS320VC5441GGU532 (169-ball BGA)

Industrial temperature range devices (–40°C to 100°C)
       TMS320VC5441APGF532 (176-pin LQFP)
       TMS320VC5441AGGU532 (169-ball BGA)

The TMS320VC5441 fixed-point digital signal processor is a quad-core solution running at 532-MIPS performance. The 5441 consists of four DSP subsystems with shared program memory. Each subsystem consists of one TMS320C54x™ DSP core, 32K-word program/data DARAM, 64K-word data DARAM, three multichannel buffered serial ports, DMA logic, one watchdog timer, one general-purpose timer, and other miscellaneous circuitry.

The 5441 also contains a host-port interface (HPI) that allows the 5441 to be viewed as a memory-mapped peripheral to a host processor.

Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5441 includes the control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the 5441 has a total of 256K words of shared program memory (128K words shared by subsystems A and B, and another 128K words shared by subsystems C and D).

The 5441 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over IP subsystems. It is designed to maintain the current modem architecture with minimal hardware and software impacts, thus maximizing reuse of existing modem technologies and development efforts.

The 5441 is offered in two temperature ranges and individual part numbers are shown below. (Please note that the industrial temperature device part numbers do not follow the typical numbering tradition.)

Commercial temperature devices (0°C to 85°C)
       TMS320VC5441PGF532 (176-pin LQFP)
       TMS320VC5441GGU532 (169-ball BGA)

Industrial temperature range devices (–40°C to 100°C)
       TMS320VC5441APGF532 (176-pin LQFP)
       TMS320VC5441AGGU532 (169-ball BGA)

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技術資料

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート TMS320VC5441 Fixed-Point Digital Signal Processor データシート (Rev. F) 2008年 10月 22日
* エラッタ TMS320VC5441 Digital Signal Processor Silicon Errata (Rev. C) 2006年 4月 6日
ユーザー・ガイド TMS320C54x Chip Support Library API Reference Guide (Rev. D) 2003年 5月 5日
アプリケーション・ノート Using Boundary Scan on the TMS320VC5441 (Rev. A) 2002年 4月 15日
ユーザー・ガイド TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) 2001年 3月 31日
ユーザー・ガイド TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) 2001年 1月 31日
ユーザー・ガイド TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) 2001年 1月 31日
ユーザー・ガイド TMS320C54x DSP Applications Guide Reference Set Volume 4 1996年 10月 1日

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価ボード

TMDSDSK5416 — C5416 DSP スタータ・キット(DSK)

TMS320C5416 DSP スタータ・キット(DSK)は、TI の TMS320C54x DSP をベースにした低消費電力アプリケーションの開発にかかる期間を短縮するように設計された、低コストの開発プラットフォームです。このキットには、USB 通信やプラグ・アンド・プレイ機能など、性能を向上する新機能が含まれており、設計の初心者であっても熟練者であっても、革新的な製品設計をすぐに開始できるようになっています。

C5416 DSK には、DSK (...)

デバッグ・プローブ

TMDSEMU560V2STM-U — XDS560™ ソフトウェア v2 システム・トレース USB デバッグ・プローブ

XDS560v2 は、XDS560™ ファミリのデバッグ・プローブの中で最高の性能を達成し、従来の JTAG 規格 (IEEE1149.1) と cJTAG (IEEE1149.7) の両方をサポートしています。シリアル・ワイヤ・デバッグ (SWD) をサポートしていないことに注意してください。

すべての XDS デバッグ・プローブは、組み込みトレース・バッファ (ETB) を搭載しているすべての ARM プロセッサと DSP プロセッサで、コア・トレースとシステム・トレースをサポートしています。ピン経由でコア・トレースを実行する場合、XDS560v2 PRO TRACE が必要です。

(...)

デバッグ・プローブ

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

シミュレーション・モデル

VC5441 GGU BSDL Model

SPRM079.ZIP (12 KB) - BSDL Model
シミュレーション・モデル

VC5441 PGF BSDL Model

SPRM080.ZIP (12 KB) - BSDL Model
設計ツール

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TI は複数の企業と提携し、TI の各種プロセッサを使用した幅広いソフトウェア、ツール、SOM (システム・オン・モジュール) を提供する方法で、量産までの開発期間短縮を支援しています。この検索ツールをダウンロードすると、サード・パーティーの各種ソリューションを手早く参照し、お客様のニーズに適したサード・パーティーを見つけることができます。掲載されている各種ソフトウェア、ツール、モジュールの製造と管理を実施しているのは、TI (テキサス・インスツルメンツ) ではなく独立系サード・パーティー各社です。

検索ツールは、製品の種類別に以下の分類を採用しています。

  • ツールに該当するのは、IDE (...)
パッケージ ピン数 ダウンロード
LQFP (PGF) 176 オプションの表示

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 材質成分
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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