製品の詳細

CPU Arm Cortex-R4F Frequency (MHz) 180 ADC 2 x 12-Bit (24ch) GPIO 144 UART 2 Number of I2Cs 1 TI functional safety category Functional Safety-Compliant Operating temperature range (C) -40 to 125, -55 to 125
CPU Arm Cortex-R4F Frequency (MHz) 180 ADC 2 x 12-Bit (24ch) GPIO 144 UART 2 Number of I2Cs 1 TI functional safety category Functional Safety-Compliant Operating temperature range (C) -40 to 125, -55 to 125
NFBGA (GWT) 337 256 mm² 16 x 16
  • High-Performance Microcontroller for Safety-
    Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM interfaces
    • Built-In Self-Test for CPU and On-chip RAMs
    • Error Signaling Module with Error Pin
    • Voltage and Clock Monitoring
  • ARM® Cortex – R4F 32-Bit RISC CPU
    • Efficient 1.66 DMIPS/MHz with 8-Stage Pipeline
    • FPU with Single- and Double-Precision
    • 12-Region Memory Protection Unit
    • Open Architecture with Third-Party Support
  • Operating Conditions
    • Up to 180-MHz System Clock
    • Core Supply Voltage (VCC): 1.2 V Nominal
    • I/O Supply Voltage (VCCIO): 3.3 V Nominal
    • ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
    • IP Modules GBD for –40°C to 125°C Only
      includes Flash, MibADC timings, nPORRST,
      N2HET, and FlexRay
  • Integrated Memory
    • 3MB of Program Flash With ECC
    • 256KB of RAM With ECC
    • 64KB of Flash With ECC for Emulated
      EEPROM
  • 16-Bit External Memory Interface
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt Timer (RTI) OS Timer
    • 96-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Control Packets
    • Parity Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked-Loop
    (FMPLL) with Built-In Slip Detector
  • Separate Nonmodulating PLL
  • IEEE 1149.1 JTAG, Boundary Scan and ARM
    CoreSight™ Components
  • JTAG Security Module
  • Trace and Calibration Capabilities
    • Embedded Trace Macrocell (ETM-R4)
    • Data Modification Module (DMM)
    • RAM Trace Port (RTP)
    • Parameter Overlay Module (POM)
  • Multiple Communication Interfaces
    • 10/100 Mbps Ethernet MAC (EMAC)
      • IEEE 802.3 Compliant (3.3-V I/O only)
      • Supports MII, RMII and MDIO
    • FlexRay Controller with Two Channels
      • 8 KB message RAM with Parity Protection
      • Dedicated Transfer Unit (FTU)
    • Three CAN Controllers (DCANs)
      • 64 Mailboxes, Each with Parity Protection
      • Compliant to CAN Protocol Version 2.0B
    • Local Interconnect Network (LIN) Interface
      Controller
      • Compliant to LIN Protocol Version 2.1
      • Can be Configured as a Second SCI
    • Standard Serial Communication Interface (SCI)
    • Inter-Integrated Circuit (I2C)
    • Three Multibuffered Serial Peripheral Interfaces
      (MibSPIs)
      • 128 Words with Parity Protection Each
    • Two Standard Serial Peripheral Interfaces
      (SPIs)
  • Two High-End Timer Modules (N2HETs)
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM with Parity Protection
      Each
    • Each N2HET Includes Hardware Angle
      Generator
    • Dedicated Transfer Unit with MPU for Each
      N2HET (HTU)
  • Two 10- or 12-bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels Shared with ADC1
    • 64 Result Buffers with Parity Protection Each
  • Sixteen General-Purpose Input/Output Pins (GPIO)
    Capable of Generating Interrupts
  • Package
    • 337-Ball Grid Array (SnPb) (GWT)
  • High-Performance Microcontroller for Safety-
    Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM interfaces
    • Built-In Self-Test for CPU and On-chip RAMs
    • Error Signaling Module with Error Pin
    • Voltage and Clock Monitoring
  • ARM® Cortex – R4F 32-Bit RISC CPU
    • Efficient 1.66 DMIPS/MHz with 8-Stage Pipeline
    • FPU with Single- and Double-Precision
    • 12-Region Memory Protection Unit
    • Open Architecture with Third-Party Support
  • Operating Conditions
    • Up to 180-MHz System Clock
    • Core Supply Voltage (VCC): 1.2 V Nominal
    • I/O Supply Voltage (VCCIO): 3.3 V Nominal
    • ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
    • IP Modules GBD for –40°C to 125°C Only
      includes Flash, MibADC timings, nPORRST,
      N2HET, and FlexRay
  • Integrated Memory
    • 3MB of Program Flash With ECC
    • 256KB of RAM With ECC
    • 64KB of Flash With ECC for Emulated
      EEPROM
  • 16-Bit External Memory Interface
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt Timer (RTI) OS Timer
    • 96-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Control Packets
    • Parity Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked-Loop
    (FMPLL) with Built-In Slip Detector
  • Separate Nonmodulating PLL
  • IEEE 1149.1 JTAG, Boundary Scan and ARM
    CoreSight™ Components
  • JTAG Security Module
  • Trace and Calibration Capabilities
    • Embedded Trace Macrocell (ETM-R4)
    • Data Modification Module (DMM)
    • RAM Trace Port (RTP)
    • Parameter Overlay Module (POM)
  • Multiple Communication Interfaces
    • 10/100 Mbps Ethernet MAC (EMAC)
      • IEEE 802.3 Compliant (3.3-V I/O only)
      • Supports MII, RMII and MDIO
    • FlexRay Controller with Two Channels
      • 8 KB message RAM with Parity Protection
      • Dedicated Transfer Unit (FTU)
    • Three CAN Controllers (DCANs)
      • 64 Mailboxes, Each with Parity Protection
      • Compliant to CAN Protocol Version 2.0B
    • Local Interconnect Network (LIN) Interface
      Controller
      • Compliant to LIN Protocol Version 2.1
      • Can be Configured as a Second SCI
    • Standard Serial Communication Interface (SCI)
    • Inter-Integrated Circuit (I2C)
    • Three Multibuffered Serial Peripheral Interfaces
      (MibSPIs)
      • 128 Words with Parity Protection Each
    • Two Standard Serial Peripheral Interfaces
      (SPIs)
  • Two High-End Timer Modules (N2HETs)
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM with Parity Protection
      Each
    • Each N2HET Includes Hardware Angle
      Generator
    • Dedicated Transfer Unit with MPU for Each
      N2HET (HTU)
  • Two 10- or 12-bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels Shared with ADC1
    • 64 Result Buffers with Parity Protection Each
  • Sixteen General-Purpose Input/Output Pins (GPIO)
    Capable of Generating Interrupts
  • Package
    • 337-Ball Grid Array (SnPb) (GWT)

The TMS570LS3137-EP device is a high-performance microcontroller family for safety systems. The safety architecture includes the following:

  • Dual CPUs in lockstep
  • CPU and memory built-in self-test (BIST) logic
  • ECC on both the flash and the data SRAM
  • Parity on peripheral memories
  • Loopback capability on peripheral I/Os

The TMS570LS3137-EP device integrates the ARM Cortex-R4F Floating-Point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.

The TMS570LS3137-EP device has 3MB of integrated flash and 256KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word and double-word modes.

The TMS570LS3137-EP device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit analog-to-digital converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode.

The device has multiple communication interfaces: three MibSPIs, , one LIN, one SCI, three DCANs, one I2C. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.

The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the global clock module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The DMA controller has 16 channels, 32 control packets and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the DMA.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals or FPGA devices.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built in ARM Cortex-R4F CoreSight debug features an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows parameters and tables to be dynamically calibrated against production code without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.

With integrated safety features and a wide choice of communication and control peripherals, the device is an ideal solution for high-performance real-time control applications with safety-critical requirements.

The TMS570LS3137-EP device is a high-performance microcontroller family for safety systems. The safety architecture includes the following:

  • Dual CPUs in lockstep
  • CPU and memory built-in self-test (BIST) logic
  • ECC on both the flash and the data SRAM
  • Parity on peripheral memories
  • Loopback capability on peripheral I/Os

The TMS570LS3137-EP device integrates the ARM Cortex-R4F Floating-Point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.

The TMS570LS3137-EP device has 3MB of integrated flash and 256KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word and double-word modes.

The TMS570LS3137-EP device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit analog-to-digital converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode.

The device has multiple communication interfaces: three MibSPIs, , one LIN, one SCI, three DCANs, one I2C. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.

The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the global clock module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The DMA controller has 16 channels, 32 control packets and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the DMA.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals or FPGA devices.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built in ARM Cortex-R4F CoreSight debug features an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows parameters and tables to be dynamically calibrated against production code without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.

With integrated safety features and a wide choice of communication and control peripherals, the device is an ideal solution for high-performance real-time control applications with safety-critical requirements.

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技術資料

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34 資料すべて表示
種類 タイトル 英語版のダウンロード 日付
* データシート TMS570LS3137-EP 16- and 32-Bit RISC Flash Microcontroller データシート (Rev. D) 2015年 2月 20日
* エラッタ TMS570LS31x/21x Microcontroller Silicon Errata (Silicon Revision C) (Rev. G) 2016年 5月 31日
* エラッタ TMS570LS31x/21x Microcontroller Silicon Errata (Silicon Revision D) (Rev. B) 2016年 5月 31日
* ユーザー・ガイド TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (Rev. C) 2018年 3月 1日
* VID TMS570LS3137-EP VID V6213629 2016年 6月 21日
* 放射線と信頼性レポート TMS5703137CGWTMEP Reliability Report 2015年 2月 6日
* 放射線と信頼性レポート TMS5703137CGWTQEP Reliability Report 2014年 12月 22日
技術記事 5 ways high-performance MCUs are reshaping the industry 2021年 7月 12日
セレクション・ガイド Enhanced Product Selection Guide (Rev. C) 2021年 6月 30日
その他の技術資料 SafeTI™ Hercules™ Diagnostic Library Test Automation Unit User Guide (Rev. B) 2020年 1月 9日
ユーザー・ガイド HALCoGen-CSP User's Guide (Rev. C) 2020年 1月 8日
ユーザー・ガイド SafeTI Hercules Diagnostic Library -TAU Installation Guide (Rev. B) 2020年 1月 8日
その他の技術資料 SafeTI-HALCoGen-CSP 04.07.01 (Rev. C) 2020年 1月 8日
ユーザー・ガイド SafeTI-HALCoGen-CSP Installation Guide (Rev. B) 2020年 1月 8日
ユーザー・ガイド SafeTI Hercules Diagnostic Library CSP Without LDRA 2019年 10月 29日
アプリケーション・ノート HALCoGen Ethernet Driver With lwIP Integration Demo and Active Webserver Demo 2019年 9月 13日
アプリケーション・ノート CAN Bus Bootloader for Hercules Microcontrollers 2019年 8月 21日
アプリケーション・ノート SafeTI HALCoGen CSP Without LDRA Release_Notes 2019年 8月 19日
ユーザー・ガイド SafeTI Hercules Diagnostic Library - Without LDRA Installation Guide 2019年 8月 19日
ユーザー・ガイド SafeTI-HALCoGen-CSP Without LDRA Installation Guide 2019年 8月 19日
ユーザー・ガイド SafeTI-HALCoGen-CSP Without LDRA User's Guide 2019年 8月 19日
ユーザー・ガイド SafeTI™ Hercules™ Diag Lib Test Automation Unit Without LDRA User's Guide 2019年 8月 19日
アプリケーション・ノート Sharing FEE Blocks Between Boot Loader and Application 2017年 11月 7日
アプリケーション・ノート Sharing Exception Vectors on Hercules™ Based Microcontrollers 2017年 3月 27日
アプリケーション・ノート How to Create a HalCoGen Based Project For CCSv4.x (Rev. B) 2016年 8月 9日
アプリケーション・ノート Using the CRC Module on Hercules™-Based Microcontrollers 2016年 8月 4日
アプリケーション・ノート Using the SPI as an Extra UART Transmitter 2016年 7月 26日
アプリケーション・ノート High Speed Serial Bus Using the MibSPIP Module on Hercule-Based MCUs 2016年 4月 22日
アプリケーション・ノート Triggering ADC Using Internal Timer Events on Hercules MCUs 2015年 10月 19日
アプリケーション・ノート Continuous Monitor of the PLL Frequency With the DCC 2015年 7月 24日
ホワイト・ペーパー Foundational Software for Functional Safety 2015年 5月 12日
アプリケーション・ノート Sine Wave Generation Using PWM With Hercules N2HET and HTU 2015年 5月 12日
アプリケーション・ノート Triangle/Trapezoid Wave Generation Using PWM With Hercules N2HET 2015年 5月 1日
アプリケーション・ノート Hercules SCI With DMA 2015年 3月 22日

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デバッグ・プローブ

TMDSEMU200-U — Spectrum Digital XDS200 USB エミュレータ

Spectrum Digital XDS200 は、TI のプロセッサを対象とする最新の XDS200 デバッグ・プローブ(エミュレータ)ファミリの最初のモデルです。XDS200 ファミリは、超低コストの XDS100 と高性能の XDS560v2 の間で、低コストと高性能の最適バランスを実現します。また、すべての XDS デバッグ・プローブは、ETB(Embedded Trace Buffer、組込みトレース・バッファ)を搭載したすべての ARM と DSP プロセッサに対し、コア・トレースとシステム・トレースをサポートしています。

Spectrum Digital XDS200 は、TI 20 ピン・コネクタ(TI 14 ピン、ARM 10 ピン、ARM 20 ピンを接続するための複数のアダプタ付属)とホスト側の USB 2.0 (...)

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デバッグ・プローブ

TMDSEMU560V2STM-U — Blackhawk XDS560v2 システム・トレース USB エミュレータ

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

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デバッグ・プローブ

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

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開発キット

TMDS570LS31HDK — TMS570LS31x Hercules 開発キット

The TMS570LS31 Hercules™ Development Kit is based on the IEC 61508 SIL 3 and ISO 26262 ASIL D certified TMS570LS3137 and is ideal for getting started on development with TMS570LS31x/21x series of the Hercules TMS570 microcontroller family. The development board features RJ45 10/100 Ethernet, two CAN (...)

IDE (統合開発環境)、構成機能、またはデバッガ

CCSTUDIO-SAFETY — Hercules™セーフティ MCU Code Composer Studio(CCStudio)統合開発環境(IDE)

Code Composer Studio は、TI のマイコンと組込みプロセッサ・ポートフォリオをサポートする統合開発環境(IDE)です。Code Composer Studio は、組込みアプリケーションの開発およびデバッグに必要な一連のツールで構成されています。最適化 C/C++ コンパイラ、ソース・コード・エディタ、プロジェクト・ビルド環境、デバッガ、プロファイラなど、多数の機能が含まれています。直感的な IDE には、アプリケーションの開発フローをステップごとに実行できる、単一のユーザー・インターフェイスが備わっています。使い慣れたツールとインターフェイスにより、ユーザーは従来より迅速に作業を開始できます。Code Composer Studio は、Eclipse ソフトウェア・フレームワークの利点と、TI の先進的な組込みデバッグ機能の利点を組み合わせ、組込み分野のデベロッパーにとって豊富な機能を備えた魅力的な開発環境を実現します。 

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パッケージ ピン数 ダウンロード
NFBGA (GWT) 337 オプションの表示

購入と品質

含まれる情報:
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  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
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  • MTBF/FIT の推定値
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  • 認定試験結果
  • 継続的な信頼性モニタ試験結果

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