TPS7A8101

The ADS58J64EVM is an evaluation board used to evaluate the ADS58J64 Integrated Receiver from Texas Instruments. The ADS58J64 is a low power, 14-bit, 500-MSPS, quad channel telecom receiver with a buffered analog input. The device supports JESD204B interface and data rates up to 10Gbps. The EVM has (...)

• Transformer-coupled signal input network, allows a single-ended signal source to the EVM
• On board system clock generator (LMK04828) generates the FPGA reference clock, ADC sampling clock and SYSREFs for the high-speed JESD204B serial interface
• Default transformer-coupled clock input network enables (...)

The DAC38RF80EVM is the circuit board for evaluating DAC38RF80/84/90 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate. It is designed to work with the FPGA-based pattern generator card TSW14J56EVM (Rev B and up). The available (...)

• Allows evaluation of DAC38RF80/84/90 up to 9-GSPS sampling rate
• Supports up to 12.5-Gbps SerDes signaling rate across FMC
• Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
• AC-coupled output with 2:1 impedance transformer for (...)

• DAC38RF82/83/85/93 を最大 9GSPS のサンプリング・レートで評価可能
• FMC 経由で最大 12.5Gbps の SerDes シグナリング・レートをサポート
• VCO を 2 個搭載した 低位相ノイズのオンチップ PLL を内蔵し、システム・クロック生成を簡素化。外部クロック・モードもサポート。
• AC 結合型の差動出力と、平衡型から不平衡型への変換のためのオンボード 2:1 インピーダンス・トランス
• 使いやすいソフトウェア・インターフェイスとデータ・パターン生成ツール

• Allows evaluation of DAC38RF86 or DAC38RF96 up to 9-GSPS sampling rate
• Supports up to 12.5-Gbps SerDes signaling rate across FMC
• Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
• AC-coupled output with integrated impedance transformer (...)

The DAC38RF89 evaluation module (EVM) is the circuit board for evaluating DAC38RF89 digital-to-analog converters (DACs). The DAC38RFEVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC (...)

• Allows evaluation of DAC38RF89 up to 9-GSPS sampling rate
• Supports up to 12.5-Gbps SerDes signaling rate across FMC
• Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
• AC-coupled output with integrated impedance transformer (DAC38RF89) for (...)

DCA1000 評価基板 (EVM) は、TI の AWR と IWR の各レーダー・センサ EVM から取得する 2 レーンおよび 4 レーンの LVDS (低電圧差動信号伝送) トラフィックに対して、リアルタイム・データ・キャプチャとストリーミングを実施できます。1Gbps イーサネットを使用して、MMWAVE-STUDIO ツールを実行している PC 宛にこのデータをリアルタイムでストリーミング送信し、キャプチャと可視化を実行した後、選定したアプリケーションにその結果を渡し、データ処理とアルゴリズムの開発を進めることができます。

• ラボとモバイル・コレクションのシナリオをサポート
• AWR/IWR の各レーダー・センサから LVDS データをキャプチャ
• 1Gbps イーサネットを経由して出力をリアルタイムでストリーミング送信
• 複数のオンボード・スイッチまたは GUI / ライブラリを使用して制御

• Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz  at 122.88 MHz output frequency
• Integrated Loopfilter support easy prototyping
• 0.9 W typical power consumption for 10 outputs at 122.88 MHz
• Jumper configurable supplies with on-board LDOs and DCDC converters
• GUI platform for full access (...)

• Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz at 122.88 MHz output frequency
• Integrated Loopfilter support easy prototyping
• 1.2 W typical power consumption for 16 outputs at 122.88 MHz
• Jumper configurable supplies with on-board LDOs and DCDC converters
• GUI platform for full access (...)

The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)

• Dual DPLLs with programmable bandwidths and Analog PLLs for frequency translation
• 4 clock inputs supporting hitless switching and holdover
• 8 differential or 16 LVCMOS output clocks or combination of both 
• On-chip EEPROM for custom start-up clock clocks
• Flexible oscillator options: onboard XOs, TCXO, or (...)

• One Digital PLL (DPLL) with programmable bandwidths and Two Fractional Analog PLLs (APLLs) for Flexible Clock Generation
• Two reference inputs to the DPLL supporting hitless switching & holdover
• Eight output clocks with 50-fs RMS phase jitter (12 kHz to 20 MHz)
• On-chip EEPROM for custom start-up clock (...)

• Input Voltage as low as 2.2V
• 170mV dropout @ 1A
• Adjustable output from 0.8V to 6.0V
• Protections: Over current and Over temperature
• Enable pin
• Wide-Bandwidth High PSRR
• Low-Noise 3mm x 3mm SON-8 DRB Package