CDCLVD2106EVM
CDCLVD2106 評価モジュール
CDCLVD2106EVM
概要
The CDCLVD1212/CDCLVD2106 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators that can provide the LVDS common-mode voltage to the device inputs. The evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVD1212 or CDCLVD2106. However, this EVM can also be used for customers interested in the CDCLVD1216 or CDCLVD2108 as well. This fully assembled and factory-tested evaluation board allows complete validation of device functionalities. For optimum performance, the board is equipped with SMA connectors and well-controlled 50-ohm impedance microstrip transmission lines.
特長
- Easy-to-use evaluation board to fan out low-phase noise clocks
- Easy device setup
- Fast configuration
- Control pins configurable through jumpers
- Board powered at 2.5 V
- Single-ended or differential input clocks
- Device supports twelve LVDS outputs, EVM supports four LVDS outputs
クロック・バッファ
技術資料
| 種類 | タイトル | 英語版のダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| 証明書 | CDCLVD2106EVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 | ||||
| ユーザー・ガイド | Low Additive Jitter, Twelve LVDS Outputs Clock Buffer Evaluation Board | 2010年 9月 1日 |