The XDS560v2 PRO TRACE Receiver is the latest model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The XDS560v2 PRO TRACE Receiver supports the same features as the XDS560v2 System Trace family (USB version, USB & Ethernet version) and adds support for core pin trace (instruction and data) in its large external memory buffer. Available for selected TI devices, this external memory buffer captures all instructions that are executed by a processor or core to allow analyzing hard-to-find issues in an embedded system. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB).
The XDS560v2 PRO TRACE Receiver connects to the target board via either a MIPI HSPT 60-pin or a TI 60-pin connector (with a supplied adapter) and to the host PC via either USB2.0 High speed (480Mbps) or Ethernet 10/100Mbps. It also requires a license of Code Composer Studio™ IDE running on the host PC.
XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity microcontrollers.
The XDS560v2 is the first of the XDS560 family of debug probes to provide System Trace (STM) capability, a type of Trace that monitors the entire device by capturing system events such as the state of processing cores, internal buses and peripherals. Most XDS560v2 models feature also System Pin Trace, a mode where the System Trace data is sent to an external memory buffer (128MB) inside the XDS560v2 to allow capturing larger number of system events. The System Pin Trace data connection requires additional wiring to the JTAG connector.
The XDS560v2 PRO TRACE is the second generation of the XDS560 family of debug probes to feature Core Pin Trace (Instruction and Data), a type of Trace that captures all instructions executed by a core and sends them to an external memory buffer (1GB) inside the XDS560v2 PRO TRACE. The Core Pin Trace does not intrude in the real-time behaviour of the system and allows capturing a larger number of instructions. The Core Pin Trace data connection requires additional wiring to the JTAG connector.
To accommodate for all types of Pin Trace (Instruction and System), all XDS560v2 variants feature a standard 60-pin MIPI HSPT connector as the primary JTAG connectivity to the target. In addition to that, all variants also feature modular target adapters for TI and ARM standard JTAG connectors (the offer of adapters varies per model).
The XDS560v2 supports the traditional IEEE1149.1 (JTAG) emulation as well as IEEE1149.7 (cJTAG) and operates with JTAG interface levels from +1.2V to +4.1V.
Compact JTAG (cJTAG) is a major improvement over the traditional JTAG, as it supports all its features while using only two pins, and is available in selected TI wireless connectivity microcontrollers.
All XDS560v2 models support either USB2.0 High speed (480Mbps) or Ethernet 10/100Mbps, with some models supporting both. Also, some models support PoE (Power over Ethernet) for added flexibility.
The XDS560v2 System Trace unit is fully compatible with TI’s Code Composer Studio IDE. This combination gives a complete hardware development environment which includes an Integrated Debug Environment, Compiler, and full hardware debugging and Trace capability (on selected devices) of TI microcontrollers, processors and wireless connectivity microcontrollers.
Other XDS products:
XDS110 EnergyTrace HDR
XDS560v2 System Trace with USB
XDS560v2 System Trace with USB and Ethernet